Hi all, I want to know if is possible to harden multiple modules as a macro. For example, I'm working on a FIFO, and that memory is based on an 8x1024 SRAM + a management logic that allows working as a FIFO. When I harden the module as a core the workflow end successfully, but when I harden it as a macro the workflow fails with LVS errors, that due to OpenLane detecting that the power and ground pins are not connected. So the question is, can I harden a module as a macro that internally has a macro, as the figure shows?

Hi @Matt Venn, Thanks for your quick answer, in the attached example their configuration file is marked as a core. I would like to know if can I create it as a macro or if can I use the core design as a macro (as instantiation in other project)

ok, sorry didn't see that. Yes as far as I know, the issue is to do with the PDN

Thanks, Matt, your comments, videos, or post always save me or help me with some issues. I saw the config variables and I think the key is the variable "FP_PDN_CHECK_NODES" to avoid the LVS error at the macro level, when I have time I will test it, and I commented you the results.

@Emilio Baungarten What LVS errors are being flagged? It is possible do create a hierarchy of hard macros using openlane, but for each hierarchy the top metal layer is usually reduced by 1. So the top metal for

user_project_wrapper

is metal5, the top metal for the top hard macro is metal4, the top metal for any macros in that macro would be metal3. You might be able to get away with one more level.

Well i tried with FP_PDN_CHECK_NODES:0 and i get the same error. @Mitch Bailey i attach the LVS log, verilog files and cofig file. Note that the error happens when i set DESIGN_IS_CORE as false.

@Emilio Baungarten I believe the

FP_PDN_CHECK_NODES = 0

doesn’t fix any errors, it just skips them at the routing stage and they show up in LVS. Looking at the sram macro layout, it looks like the top layer is metal4, so power will be routed on metal5. Since your FIFO macro has

RT_MAX_LAYER=met4

, there’s no way to connect at this level. In this case,

FP_PDN_CHECK_NODES = 0

is probably the correct setting. It may be possible to add top level pins to the FIFO macro so that vias will drop through the hierarchy and connect metal4 in the sram to metal5 in the top hierarchy. You might be able to get LVS to pass if you change the extraction parameter from

extract unique

to

extract unique notopports

. If you want to post your gds and gate level verilog, I’ll see if I can get something to work.

How can i change "extract unique" to "extract unique notopports"? "If you want to post your gds and gate level verilog, I’ll see if I can get something to work." of course, I attach the files

I strive to have 0 lvs but sometimes it's impossible. We just had a tapeout with many errors due to incorrect extraction by magic.

@Matt Venn There are some tricks to get magic to extract correctly. Do you want to open another thread to discuss?