thanks for the call afternoon folks, this is where...
# generative-aih
Hammond
06/02/2023, 11:02 PMthanks for the call afternoon folks, this is where I got to when the toolflow failed:
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[STEP 36]
[INFO]: Running Circuit Validity Checker ERC (log: ../home/hammond/Documents/vivado_projs/qtcore-C1/openlane/user_proj_example/runs/23_06_02_17_45/logs/signoff/36-erc_screen.log)...
[INFO]: Saving current set of views in '../home/hammond/Documents/vivado_projs/qtcore-C1/openlane/user_proj_example/runs/23_06_02_17_45/results/final'...
[INFO]: Saving current set of views in '../home/hammond/Documents/vivado_projs/qtcore-C1'...
[INFO]: Saving runtime environment...
[INFO]: Generating final set of reports...
[INFO]: Created manufacturability report at '../home/hammond/Documents/vivado_projs/qtcore-C1/openlane/user_proj_example/runs/23_06_02_17_45/reports/manufacturability.rpt'.
[INFO]: Created metrics report at '../home/hammond/Documents/vivado_projs/qtcore-C1/openlane/user_proj_example/runs/23_06_02_17_45/reports/metrics.csv'.
[WARNING]: There are max fanout violations in the design at the typical corner. Please refer to '../home/hammond/Documents/vivado_projs/qtcore-C1/openlane/user_proj_example/runs/23_06_02_17_45/reports/signoff/25-rcx_sta.slew.rpt'.
[INFO]: There are no hold violations in the design at the typical corner.
[ERROR]: There are setup violations in the design at the typical corner. Please refer to '../home/hammond/Documents/vivado_projs/qtcore-C1/openlane/user_proj_example/runs/23_06_02_17_45/reports/signoff/25-rcx_sta.max.rpt'.
[INFO]: Saving current set of views in '../home/hammond/Documents/vivado_projs/qtcore-C1/openlane/user_proj_example/runs/23_06_02_17_45/results/final'...
[INFO]: Generating final set of reports...
[INFO]: Created manufacturability report at '../home/hammond/Documents/vivado_projs/qtcore-C1/openlane/user_proj_example/runs/23_06_02_17_45/reports/manufacturability.rpt'.
[INFO]: Created metrics report at '../home/hammond/Documents/vivado_projs/qtcore-C1/openlane/user_proj_example/runs/23_06_02_17_45/reports/metrics.csv'.
[INFO]: Saving runtime environment...
[ERROR]: Flow failed.
[INFO]: The failure may have been because of the following warnings:
[WARNING]: There are max fanout violations in the design at the typical corner. Please refer to '../home/hammond/Documents/vivado_projs/qtcore-C1/openlane/user_proj_example/runs/23_06_02_17_45/reports/signoff/25-rcx_sta.slew.rpt'.a
Andrew Wright
06/02/2023, 11:30 PM@Hammond So that's a complex digital logic path that looks like it is not able to run in a single clock cycle at 33Mhz. Is this a large adder or multiplier by any chance? It seems like a very large number of cells to go through without a register stage in a single cycle. (All the reported failing paths seem to be similar in architecture)
Andrew Wright
06/02/2023, 11:31 PMOr is it a false or unused path?
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Hammond
06/02/2023, 11:48 PMif it's passing through the 256-byte DFFRAM this could be that long I suppose?
Hammond
06/02/2023, 11:49 PMi'm not super familiar with the intricacies of DFFRAM but I guess they could make it fairly slow
a
Andrew Wright
06/02/2023, 11:59 PMHow wide and deep is the DFFRAM?
Andrew Wright
06/03/2023, 12:00 AMAlso Does your target frequency matter or could you run slower and still be successful? (Since this is a setup time problem it can be fixed by just reducing the target freq.
h
Hammond
06/03/2023, 12:05 AMi am quite happy to just reduce the frequency
Hammond
06/03/2023, 12:06 AMthe DFFRAM is 256 deep, 8 bits wide
Hammond
06/03/2023, 1:24 AMwhat are all the places that I need to change to make the clock slower? The two SDCs and the config.jsons for the user_proj_example and user_project_wrapper? anywhere else?