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Hi, <@U016EM8L91B> <@U01819B63HP>, I would like to ask about I-V curves and hot carrier effects in s...
# analog-design
y
Hi, @Tim Edwards @Stefan Schippers, I would like to ask about I-V curves and hot carrier effects in subthreshold region. I found the I-V curve shows exponential behavior, in particular, in the case of PFETs. Is it because of the hot carriers? However, bulk currents appear to be very small. Is there any way to check with simulation to see if the circuit is protected against the effects of hot carriers?
y
It looks like the drain (3.0V) of your PMOS is higher voltage than the source (1.8V)
Also you probably want to use the sweeping voltage source of PMOS between gate and source, not gate and ground
Actually, you can ignore my first comment, I see the control block sweeps V1 between 0 and 1.8
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l
You must use 
.option gmin=1e-18
for more accuracy at those small currents, otherwise it will be too linear. Try to normalize your currents before plotting by dividing it by a measure current at some voltage value.
t
@Jennifer Hasler is undoubtedly the best expert around for understanding hot carrier effects in subthreshold. My biggest question would be whether that is modeled correctly in the sky130 bsim models.
y
Thank you very much, @Luis Henrique Rodovalho. I reran the simulation using .option gmin=1e-18. However, the result seems to be the same. Normalizing the plot does not change the result, does it? Thank you for responce, @Tim Edwards. Prof. Gert Cauwenberghs is giving a lecture about analog circuit design in subthreshold region using sky130. https://isn.ucsd.edu/courses/beng207/index.html The lecture note is here: chrome-extension://efaidnbmnnnibpcajpcglclefindmkaj/https://isn.ucsd.edu/courses/beng207/complab/hw1.pdf So it would be possible to design a circuit with subthresholds. But I am not confident. Hello, @Jennifer Hasler, I appreciate you if you give me a comment.
@yrrapt Thank you for your comments. Sorry for the lack of explanation. I would like to see the Vds dependence of the drain currents.
l
Try to plot te results in log scale. Gate current seems to be null for your experiment. The bulk currents are also small because the diodes are reverse biased
For the VDS current, you should look at the derivative. It is easy to see it in ngspice. You can use this code:
Copy code
let idn = i(v5)
let didn = deriv(idn)
plot didn
This derivative is the output conductance. You could see the output resistance by using 
let rds = 1/deriv(idn)
But if you want to normalize it, you can use 
let va = idn/deriv(idn)
y
Oh, I would like to know the raw Vds current, not its derivative. This is because I am designing an in-memory computing circuit. Here, small-signal analyis is not done.
As you mensioned, the gate current seemed to be null. So, I removed the current measurement for those currents. But, the results seem to be the same.
l
Ok, then, the best you can see from those curves is that the PFET currents are really bad and may affect your circuit. There is an second derivative that probably can break your circuit.
y
Yes, I hope to avoid the second derivative or the exponential shape. But, in my application, the shape of the curve does not matter so much unless the circuit is broken becaused of hot carrier effects.
l
The problem with this is that it is biased with voltages. Not good. The PFET transistors will be really an issue, because the currents vary a lot with VDS.
Minimum transistors length should be avoided here. First because its output resistance is really bad. Secondly, because there will be lots of problem with mismatch latter on, even for neuromorphic circuits.
And you really should use a low supply voltage. No doubt. It solves the PFET problem.
y
Yes. I am considering to use L=200 or L=300 PFETs. Those show better Vds dependence. Using a low suplly voltage is important, I agree. Thanks. But what I really want know are simulation reliability of MOS in subthreshold region and hot carrier effects in subthreshold region. I appreciate you if you give any comment on these things.
l
Well, for me, at least, the models are ok, as long as you use them with discrete sizing, such as here: https://github.com/google/skywater-pdk-libs-sky130_fd_pr/blob/f62031a1be9aefe902d6[…]d6f59b57627436/cells/nfet_01v8/sky130_fd_pr__nfet_01v8.bins.csv Outside those values, the models are not accurate.
BSIM 4.0 models, as used here, are ok for subthreshold simulation. It is not important. Almost everything works at simulation level with ideal current and voltage sources. My biggest problem with subthreshold operation, most times, is the output current. You can't just measure a real IC with normal lab equipment. See this paper here about fA circuits about the limits of subthreshold operation: https://ieeexplore.ieee.org/document/1214728
t
@Yusuke Sakemi: I was Gert's first Ph.D. student! There's a good chance that you can get your hands on a Keithley picoammeter, which is the best instrument for reading currents down in the picoamp to femtoamp range. We used to rely on them a lot for subthreshold neuromorphic designs.
y
@Luis Henrique Rodovalho Thank you for precious information! I will follow your instrucitons. Also, I am gonna try to check the output current in a real IC somehow. @Tim Edwards Wow, great! My research is greatly inspired by the work of his group. A friend of mine has the Keithley device. I will try it and share the results in the near future, hopefully.
r
Have you tried the pfet_hvt flavor? It might look more like the compliment of regular nfet
y
@Robin Tsang Thanks for comments! I simulated with pfet_hvt (bottom figures) and found a better linearity ! Do you know why pfet_hvt is better ?
r
You’re welcome. I don’t know why, it was just a guess. Good luck.
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