jeffdi
user_project_wrapper.v
in the verilog/rtl
directory of the project
4. Update the config.json
file in the openlane/user_project_wrapper
directory. This includes the references to any verilog files in addition to user_project_wrapper.v that you have in your design. Review base_user_project_wrapper.sdc
in the same directory if you need to update any timing contraints for the design.
5. From the project root directory, run make user_project_wrapper
to harden the design.
6. If your design is implementing multiple macros, see the documentation for Caravel User Project on how to implement your design.
7. See the following link for how to extend the example test bench provided for running full-chip simulation — https://caravel-user-project.readthedocs.io/en/latest/#running-full-chip-simulation
8. Update verilog/rtl/user_defines.v
. You must replace GPIO_MODE_INVALID for each gpio default configuration with a valid value from the comments in the file (see https://caravel-user-project.readthedocs.io/en/latest/#gpio-configuration)
9. Commit and push all files including gds/caravel_user_project_wrapper.gds
to your repo.
10. Create a project on the Efabless platform using this link (assuming you are already registered) — link . Make sure you set the visibility to public. Insert the URL (with the .git extension) in the GIT URL field on the form. Also include AI-design-content
in the label field (to make it easier for us to id the project) .
11. Submit a precheck job followed by a tapeout job for the project. See the ‘Manage My Submission’ button on the project detail page.
12. Complete the billing, shipping and terms and agreements and submit your project. You can resubmit and update after this up to the deadline for submission.
13. Send an email to shuttle@efabless.com with a link to your project.The Leviathan
06/02/2023, 6:19 AM