Is it int16_t not int31_t??
# generative-ait
The Leviathan
05/31/2023, 4:43 PMIs it int16_t not int31_t??
a
Andrew Wright
05/31/2023, 5:53 PMQuick question to check basics: Which Caravel tag are you currently using?
t
The Leviathan
05/31/2023, 8:01 PMgit log gives me this, the HEAD is detached
commit 414f7bce817a22d0bdef07cf2f37ef5f87d8ae6f (grafted, HEAD, tag: mpw-9c, tag: caravel_v6_0)
Author: Jeff DiCorpo <42048757+jeffdi@users.noreply.github.com>
Date: Wed Apr 26 120438 2023 -0700
update to tag mpw-9c
The Leviathan
05/31/2023, 8:23 PMAh, ChatGPT just told me, that I'm not using the cycle signal...
The Leviathan
05/31/2023, 8:23 PMLets seee
The Leviathan
05/31/2023, 8:24 PMNope, still not working
The Leviathan
05/31/2023, 8:33 PMUhmm.. Yeah, that's what I get from the Wishbone bus, which isn't what I write into the address from my C program
The Leviathan
05/31/2023, 8:33 PMmessage has been deleted
The Leviathan
05/31/2023, 8:40 PM🤔
The Leviathan
05/31/2023, 8:44 PMHmm, I think I've messed up the timing and the WB protocol 🤔
a
Andrew Wright
05/31/2023, 8:46 PMThat's the right Caravel. As soon as I get a feew mins I'll take a look at your waveform.
Andrew Wright
05/31/2023, 9:02 PMThe timing on the trailing edge of ACK and STB looks wierd. I thought they were expected to be seperated by a clock cycle for WB protocol. @jeffdi
t
The Leviathan
05/31/2023, 9:48 PMHmm, I did mess up, ChatGPT now fixed it for me
The Leviathan
05/31/2023, 9:49 PMWorks now
The Leviathan
05/31/2023, 10:00 PMHmm... now, the last value still seems to be messed up a bit... I'll keep debugging
The Leviathan
05/31/2023, 10:00 PMThe logic so far works however, all I gotta do before I can submit now is to get the wishbone interface to work with caravel
The Leviathan
05/31/2023, 10:28 PMIt's a bug with the caravel, because according to the wishbone bus specs, when the select changes, the cycle comes and so, the signal is supposed to be stable... not xxxx
The Leviathan
05/31/2023, 10:29 PMI'm disabling the SPI and GPIOs for now, maybe that causes trouble
The Leviathan
05/31/2023, 10:34 PMOMG... it's the GPIOs
a
Andrew Wright
05/31/2023, 10:35 PMIs there a signal coming from outside the design to the wishbone interface?
t
The Leviathan
05/31/2023, 10:51 PMHmm... No. I was thinking because maybe the controller messes with the addresses... the problem persists BTW.
When the data should be ready to be loaded, the data line still is xxxx
The Leviathan
05/31/2023, 10:51 PMwhich is anyway strange... shouldn't it be like either 0 or data?
The Leviathan
05/31/2023, 10:53 PMThe 2nd last value is at least defined, although wrong. It should be -2
a
Andrew Wright
05/31/2023, 10:57 PMIf you are seeing undefined values in the logic there is a timing or logical conflict in driving the value. I'd display the buss and check if it is all data bits are X. If yes, go upstream by one register and add that to the waveforms see if everything is defined. Look for the first place you can find an undefined value.
t
The Leviathan
06/01/2023, 12:17 AMGood news, it's a timing bug. When I start writing at the problematic address and only write 4 values in the for loop at once, there's no problem.
Hmm... Maybe processing the memory access takes a while 🤔