What's the maximum nwell to pwell voltage? Could I bias a deep n-well to e.g. 10V?

Aidan Medcalf

05/30/2023, 4:22 PM

What's the maximum nwell to pwell voltage? Could I bias a deep n-well to e.g. 10V?

Tim Edwards

05/31/2023, 4:15 AM

I think it's okay to 11V but I need to check. The model has a breakdown voltage parameter.

Aidan Medcalf

05/31/2023, 3:31 PM

SONOS needs +/-10.5VGS and there are diodes rated for 11V, so it seems plausible

Andrew Wright

06/01/2023, 4:46 PM

Guys the TDR says:Junction Leakage/breakdown The maximum source/drain to substrate junction voltages are restricted to the following: 1. Any HV NMOS device: 11.0 V @ 25C.

Andrew Wright

06/01/2023, 4:47 PM

This is an ABS max room temp value. Not an operating number.

Aidan Medcalf

06/01/2023, 4:48 PM

If I need a 10.5V difference, then better to split and introduce negative voltages?

Andrew Wright

06/01/2023, 4:50 PM

I 'm pretty sure that the reference info online for the memory transistor shows the combination of a negative and a positive voltage to get the state changes and stress modes done: https://skywater-pdk.readthedocs.io/en/main/rules/device-details.html#sonos-cells

Aidan Medcalf

06/01/2023, 4:52 PM

Yeah. I was hoping to avoid that for other design reasons, but I guess that's not an option. Thank you

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