Hello @Tim Edwards, I have trouble doing lvs for a simple inverter with transistor folding of the PMOS. I seems that drain|source permutation is not working. I extract the netlist from magic with

ext2spice lvs

and

ext2spice

. I run netgen with

netgen -batch lvs "inverter_schem.spice not" "inverter_layout.spice inverter" /foss/pdk/sky130A/libs.tech/netgen/sky130A_setup.tcl lvs.log

I am using the iic-osic-tools Docker.

@Alfonso Cortés Can you dump your screen output to a file and share that too?

netgen ... 2>&1 > lvs.out

Also, your layout is extracting without ports and the net names don’t match the schematic.

@Mitch Bailey Here is the output file. I don't think the ports or net names should be a problem. I extracted it without the subcircuit and the result is the same. And I have done LVS correctly to other designs before with different net names and it worked fine.

@Alfonso Cortés hmm. I’m still thinking it’s a problem with the setup file. You should see a line like

Reading setup file /foss/pdk/sky130A/libs.tech/netgen/sky130A_setup.tcl

before

Comparison output logged to file lvs.log

What do you get with this?

ls -l /foss/pdk/sky130A/libs.tech/netgen/sky130A_setup.tcl

As far as matching port names go, LVS may match topologies and give you a “clean” result, but you may experience problems implementing the circuit at a higher level.

@Mitch Bailey I get

-rw-r--r-- 1 root root 19661 May 22 17:45 /foss/pdks/sky130A/libs.tech/netgen/sky130A_setup.tcl

. The sky130A_setup.tcl file I have is the one I sent at the beginning of the thread.

I run netgen with

... /foss/pdk/...

try using

/foss/pdks/...