Hello, for a sky130 tapeout through efabless, is it alright to increase the PDK frequency in config.json?

"pdk::sky130*": {
        "FP_CORE_UTIL": 45,
        "RT_MAX_LAYER": "met4",
        "scl::sky130_fd_sc_hd": {
            "CLOCK_PERIOD": 25
        },
        "scl::sky130_fd_sc_hdll": {
            "CLOCK_PERIOD": 10
        },
        "scl::sky130_fd_sc_hs": {
            "CLOCK_PERIOD": 8
        },
        "scl::sky130_fd_sc_ls": {
            "CLOCK_PERIOD": 10,
            "SYNTH_MAX_FANOUT": 5
        },
        "scl::sky130_fd_sc_ms": {
            "CLOCK_PERIOD": 10
        }

Increasing

PL_RESIZER_SETUP_SLACK_MARGIN

,

PL_RESIZER_SETUP_SLACK_MARGIN

and

GLB_RESIZER_SETUP_SLACK_MARGIN

have no effect on my setup violations. My understanding is that the clock is either provided from the PLL or external input, so this would be fine, but I wanted to make sure

Yes if it's matching your requirements you can.

Thanks Vijayan

@Christian Duffee, Tactically yes. But it is important to understand the sources and timing of any data and clocks getting to or from your block. The Caravel wrapper design is not synthesized to 100 or 125Mhz for example so if you are using the wishbone or LA interfaces there may be issues at the boundary. The IO cells provided on Caravel can pass output signals well up to about 50Mhz, beyond that there is some attenuation. Hope this helps.

Okay, I'll make sure to keep those limits in mind. Thank you