ParkedTom
05/11/2023, 8:54 AMStefan Schippers
05/11/2023, 9:39 AMParkedTom
05/11/2023, 9:39 AMStefan Schippers
05/11/2023, 7:02 PMspice_ignore=true
attribute (or verilog_ignore=true
or vhdl_ignore=true
depending on current netlisting mode). You can select multiple objects and block-disable them. Applying the menu command again re-enables the components. Another change, now disabled elements are drawn in grey. I think this will visually help. Elements that are disabled for spice netlist are not automatically disabled for VHDL or verilog, unless you disable them for these netlist formats too.vks
05/12/2023, 7:48 AM