@ArunAshok I have created a test circuit in sky130 for a 5V charge pump, that is ~3x the supply voltage (1.8V) you can view it online starting xschem from a directory containing the sky130 xschemrc: xschem https://raw.githubusercontent.com/StefanSchippers/xschem_sky130/main/sky130_tests/tb_charge_pump.sch

@Stefan Schippers: Ah, you know how to make charge pumps! We need a design for the SONOS programming (don't know the voltage without looking it up, but I'm sure it's higher than 5V). . .

(A) is the ideal charge pump you would use if ideal diodes were available. (B) tries to approximate (A) with nfets, boosting the gate when transfering charge from the left to the right, avoiding threshold voltage losses. This topology uses nfet only. (C) uses complementary transistors, (P and N) and does not require a complex timing for the phase driver, like (B). In all cases having a "near zero Vt" transistor will help. Aggressive designs use buried well nfets to avoid body effect threshold increases that reduce the charge pump efficiency, but requiring careful well/ring taps to avoid charge injection / latchup issues. (B) and (C) topologies can be realized even with no insulated pwell, at the cost of some lower output voltage. In all designs a careful analysis must be done to ensure safe operating area (junction/oxide max voltages).

Thanks for the detailed explanation !

Programming voltages in the range 5.5-7.5 V depending on cell specs. Might need 5-8V for stress testing of the cells.

@Stefan Schippers: (B) is a classic "bucket-brigade" architecture. I have not seen the (C) CMOS version of that before.

There is a VHV (15-20V) zero Vt Nmos device in the PDK. Might not be availible on the current mask set.

@Andrew Wright: Yes, it's available. It's an extended-drain device, though, isn't it?

yes

@Andrew Wright :

sky130_fd_pr__rf_nfet_20v0_aup
sky130_fd_pr__rf_nfet_20v0_noptap_iso
sky130_fd_pr__rf_nfet_20v0_nvt_aup
sky130_fd_pr__rf_nfet_20v0_nvt_noptap_iso
sky130_fd_pr__rf_nfet_20v0_nvt_withptap
sky130_fd_pr__rf_nfet_20v0_nvt_withptap_iso
sky130_fd_pr__rf_nfet_20v0_withptap
sky130_fd_pr__rf_nfet_20v0_withptap_iso
sky130_fd_pr__rf_nfet_20v0_zvt_withptap

and

sky130_fd_pr__rf_pfet_20v0_withptap

These devices are all in

sky130_fd_pr.gds

and I'm not sure that they have models other than for these exact layouts.

Sonos: -3.8 to 6.7 nominal. Margin rtesting would require several hundred mV above and below. Burnin would be even further above and below. So I'd assume something like-4.5 to 7.0/8.5 for the charge pump to be very safe.

@Stefan Schippers @ArunAshok: Apologies for sort of hijacking your thread. . .

@Tim Edwards the (C) solution is good for high voltage / low current charge pumps. This topology has an output resistance that degrades (=increases) as load current increases. So this charge pump output voltage collapses rapidly if output current is too high. The lower the output voltage the lower the charge pump efficienty. The bucket brigade (B) has a roughly constant Rout.

@Tim Edwards No worries :)

@Tim Edwards Is there an ongoing SONOS design effort? My team is getting started on a design and we'd happily contribute (sorry to continue hijacking the thread)

@Aidan Medcalf You are not hijacking anything. As long as it is VLSI / electronics-related it's all interesting stuff to learn! 👍

@Stefan Schippers On that note, how do you insulate the p-wells in your example?

@Aidan Medcalf sky130 has the

buried

or

deep

nwell implant. It is done with a high energy n-type ion implantation (and may be some following thermal annealing), such that the peak n doping is buried deep into the p-type wafer substrate. If you draw an nwell ring and implant a deep nwell inside you insulate the inner pwell from the rest of the wafer pwell. This way you get nfets that can go negative or at very high voltages (by raising the insulated pwell to high voltage). the nwell ring (and connected deep well) must be biased at high voltage too to avoid p-n forward biasing. If insulated pwell is set negative you may bias the nwell ring at GND or VCC. Another advantage of insulated pwell nfets is that you may get rid of body bias effects (higher Vth) by keeping body and source at the same voltage. The big disadvantage of these i-pwell nfets is layout size due to the numerous tapping rings needed and parasitic capacitance in cases where you need to move the i-pwell node. I am not a process engineer so I might be mistaken on some statements. @Tim Edwards is certainly more competent on the subject.

@Stefan Schippers: You sure sound like a process engineer! : )