hello everyone i need a help for my schematic design of 6T SRAM cell. for simulation how to initialize the value for Q Qbar in EDA tools (Sky130 efabless) . or can you please let me know how to simulate for read and write operation of a 6T SRAm in sky130. do you have any suggestion or any useful link to work on magic and xschem for sky130?

use ngspice .ic command

A side note. It is very likely that body terminals for pass transistors M5 and M6 must be connected to GND

thank you so very much. do you know how to get sky130_fd_pr__special_nfet_latch instead of nfet_018v?

@Md. Sajjad Hossain Xschem does not have a symbol for this special nfet, however you can place the

nfet_01v8.sym

and change the model and dimensions and add a special

format

attribute, since this transistor does not accept the

nf

parameter. Below the correct transistor attributes to use this special nfet. Note the fixed

W=0.21

dimension, it can not be changed, while L must be between 0.075 and 0.15 (75 to 150nm)

name=M2
L=0.075
W=0.21
mult=1
format="@spiceprefix@name @@D @@G @@S @@B sky130_fd_pr__@model L=@L W=@W m=@mult"
model=special_nfet_latch
spiceprefix=X

@Stefan Schippers thank you so much.

I have never tried these transistors before. However i did run a test simulation for the special_nfet_latch with the given format string (if you do a 'q' on the transistor you should see the above set of attributes, including format="..." If this transistor simulation fails to you please send the complete netlist (the .spice file) so i can try here.

this one is the spice file for 6T sram with these special pfet nfet but it failed to run the simulation

@Md. Sajjad Hossain there are a couple of errors in the netlist, after correcting them ngspice runs with no errors. 1. all sky130_fd_pr__special_nfet_latch transistors must have W=0.21. In your examples there are some W=0.8 and some W=0.14 2. Do not use Vdd!. Use Vdd. The exclamation point is Cadence syntax for global nodes. Xschem does not use this syntax.

thank you so much. @Stefan Schippers. i am still having problem to pass the simulation test in xschem. then i tried with simple inverter. please have a look on my spice and .out file for simple inverter and the circuit. the nfet properties is name=M1 L=0.15 W=0.21 mult=1 nf=1 format="@spiceprefix@name @@D @@G @@S @@B sky130_fd_pr__@model L=@L W=@W m=@mult" model=special_nfet_pass spiceprefix=X the pfet properties isname=M1 L=0.15 W=0.21 mult=1 nf=1 format="@spiceprefix@name @@D @@G @@S @@B sky130_fd_pr__@model L=@L W=@W m=@mult" model=special_nfet_pass spiceprefix=X. its still showing errors. could you please check and let me know the solution.

The lower node of the inverter must have a label. Place a

lab_pin.sym

(the same as the one used for VCC) and give a name of

GND

or

0

.

hello @Stefan Schippers Could you please check my schematic design and output? i believe there is an issue with blb ,that is always staying low and the read operation is not working correctly. Could you please check my schematic design and simulation and let me know where the problem is? thank you sajjad

Please send the schematic (.sch) file

here is the .spce and .sch file. i wanted to verify read write operation. could you please help me on this?

There is no connection between BLb and the precharge/write net. Crossing wires do not connect by default. To make a connection delete the vertical wire, start from the precharge transistor and draw a net stopping on BLb, then from BLb draw a net to the write transistor. Same thing for BL. You must see a connecting dot if there is a connection.

thank you so much @Stefan Schippers