Hello everyone, I hope you are doing well. I would like to know the variation in SS, FF, SF, and FS corners with respect to TT corner. I know that, for example, in Slow corner, the transistor will have a slightly larger polysilicon gate than typical, but I don't know by how much.

The easiest way is to take a look at E-test and run a spice simulation.

There will be a large number of parameter variations incorporated into each corner. In sky130, for example, you'll find these in the SPICE models under

$PDK_ROOT/sky130A/libs.tech/ngspice/corners/

. It is not too productive to try to find individual contributors to the corner models. However, for example, in

ss.spice

you can find where it picks up slow corner parameters for each device, so tracking that down to

$PDK_ROOT/sky130A/libs.ref/sky130_fd_pr/spice/sky130_fd_pr__nfet_01v8__ss.pm3.spice

, you'll find the primary contributors to corner variation for the 1.8V nFET, e.g.:

toxe = 4.299402e-09

Here I'm ignoring the mismatch contribution. Compare that to the file

sky130_fd_pr__nfet_01v8__tt.pm3.spice

:

toxe = 4.148e-09

and you can see that the slow corner model has a gate oxide thickness that is 0.1514 nm thicker than the typical corner model.

@Tim Edwards Wow! That info is great! Thank you very much for your reply! It's just what I was looking for.