Hello Everyone, I have built a counter in verilog which I want to integrate with my analog circuit at the schematic level in xschem and then perform spice simulations, how do I do that, in my view I have to somehow synthesize the verilog code into a spice file and then create a symbol out of that spice file to put it on the schematic window.

Yes, if you get a spice synthetized netlist out of that verilog file you can create a symbol for it with the same input/outputs of the spice subcircuit and include directly the file. see manual here. There is also a possibility to simulate a digital subcircuit transforming all gates /ff into ngspice XSPICE equivalents. XSPICE is the digital event based subsystem of ngspice that allows to accelerate simulation of these digital blocks. Search for

spi2xspice.py

in this slack, and see @Tim Edwards flow https://github.com/RTimothyEdwards/qflow

I did transfer my synthesized verilog code to an xspice using spi2xspice.py, and the the counter model seems to be working fine except that the analog logic levels that the dac and adc bridges are using are 3.3V while I want them to be 1.8V. The ngspice manual tells to set a vcc parameter to the supply voltage to override this, but the question is where is this parameter?

I have had many difficulties using ngspice auto-bridging. If you were able, try to set

.param vcc=1.8

@Mudasir: You should be able to supply the inputs and output voltage level of the dac and adc bridges as a parameter of the models. e.g.,

.model todig_1v8 adc_bridge(in_high=1.2 in_low=0.6 rise_delay=10n fall_delay=10n)
.model toana_1v8 dac_bridge(out_high=1.8 out_low=0)

@Tim Edwards I think he is using the new 'auto bridging' feature, where if event and analog nodes have the same name bridges to/from the two domains are automatically inserted. From the manual: 12.6 Automatic insertion of bridging devices I have not had good luck with this, though.

@Stefan Schippers: He claimed to be using the

spi2xspice.py

script from qflow, which would insert explicit dac_bridge and adc_bridge components, though. I wasn't aware of the "auto-bridging" feature, so at least now I understand your response, and thanks for clarifying.

@Tim Edwards sorry, my fault, it's true the qflow inserts explicit bridges. I tried to modify a netlist generated with

spi2xspice.py

by setting event-based and analog nodes with identical names and removing explicit dac/adc bridges, but so far i didnt come to a working simulation.

@Tim Edwards I am basically using sky130 technology in my analog circuit and the same I wanted to use in the digital circuit but I think qflow has some problems with sky130, so since I just wanted a digital model right now I just synthesized the digital design in osu35 technology and built a xspice model out of that, and that's why it picked up 3.3V as the supply voltage. The model I created from spi2xspice.py seems to work fine mostly but still there are some unexpected results that are not matching with my verilog simulations, are you sure that spi2xspice.py is completely reliable in creating these digital models.

@Mudasir: It shouldn't be unless the flip-flops are mapped incorrectly. The flip-flop instances in the netlist make use an older xspice model that encodes a generic flip-flop and which can be configured for (among other things) positive and negative clock edge triggering. The sense of the clock for each flip-flop type in the PDK library is supposed to have been picked up from the liberty file passed to spi2xspice.py.

@Tim Edwards I think I got what the problem was, it was the delay caused be the gates and the flip-flops which was causing the waveforms to change around the negative edge. I had this another question regarding the unknown state within the adc bridge, I find that in my simulations when the input encounters analog values that are in the unknown region then the module outputs garbage values, but the problem is that after the analog values have settled into their valid states then the module does not behave as expected, otherwise if there are no invalid states encountered at the clock edge at any time then the module seems to be working perfectly fine,

@Mudasir: You can set ranges for what is considered a valid low or high value. But ultimately, you should get valid outputs once all inputs have transitioned to a valid state. Since xspice is event-driven, then inputs must pass one of the boundaries for a valid high or low value in order to trigger an event, so inputs that wander around the middle may not trigger digital events.

@Stefan Schippers These mixed signal simulations are taking alot of time, is there any good way to increase the speed, I already followed the ngspice manual instructions on how the speed can be enhanced.