I wanted to change the user_clock2 input clock frequency and reduce it from 10 MHz default to say 1MHz. Does anyone know how I can change it ??

The

user_clock2

signal has an independent divider from the primary clock (the wishbone clock). However, it is just a 3-bit divider, so you won't get the rate down to 1MHz. I suggest you add a clock divider after it to get the rate down to what you want.