open-source-silicon.dev

What is the minimum size of via4, actually?  The documentation <https://antmicro-skywater-pdk-docs.readthedocs.io/en/latest/rules/periphery.html#via4> says 0.8um, but `magic` insists &gt;1.18um `:drc why via4 width &lt; 1.18um (via4.1 + 2*via4.4)`  I have already enclosed via4 with sufficient met4 and met5.

via4.1=0.800µm and via4.4=0.190µm, so the equation via4.1+2*via4.4 adds up to 1.180µm

note that the magic via4 layer is a logical thing and includes both the hole (via4.1) and the surrounding metal4 (via4.4 on both sides). When editing in magic you only see a big square, but when you generate the GDS file you will see a smaller square inside a big square

OK, so the physical hole (the pillar between layers) is 0.8um W/L.  extra 0.19um on each side is needed there to make contacts.  Then, the hole-edge to hole-edge spacing can be as small as 0.8um according to `via4.2`   It makes sense now.  Thanks.

What is Linen?