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I am trying to add a constraint on the generated clock using "create_generated_clock" but the proble...
# openlane
z
I am trying to add a constraint on the generated clock using "create_generated_clock" but the problem is when I add the option of "get_ports " the tool fails to read the hierarchy name so is there any one here that can help me or tried before to do this on yosys tool
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a
you dont have a signal/port named clk_branc nvm, I am wrong
In the create a generated clock you are get_ports-ing the clk_branch port, but there are no ports with this name in the top level. Maybe try get_nets
z
I tried "get_nets' but it still doesn't work
a
post error messages
we cant debug things without any information
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