Hi, I'm having troubles with ghdl-yosys-plugin to convert my VHDL files to Verilog. When i try to convert bottom level blocks (like "alu.vhd"), it works, but when i try to convert a top level (like "po.vhd" wich has alu, muxf and regf), i get an error. Other problem is i can't convert vhdl->verilog with

yosys -m ghdl -p 'ghdl ../vhdl/constants.vhd -e constants; write_verilog constants.v'

if the

constants.vhd

just has

package ... end package

. Some suggestion to these two problems?

you probably need to include all the modules, select the top one and write verilog that