Hello everyone As, I am working on the openfasoc ...
# openfasoc
v
Hello everyone As, I am working on the openfasoc flow so, I have a doubt can anyone please tell me that what's the process of openfasoc flow for any new design ? As, I am unable to understand that how openfasoc flow will generate the analog part for any new design . Can anyone please help me ?
m
@mehdi can you help?
m
Have you followed one of the generators flow: https://openfasoc.readthedocs.io/en/latest/
v
Yes sir, I have followed the flow of temp sense generator and generated it's analog part
But now I need to do the openfasoc flow for the new design
m
Maybe you should join our Friday weekly meeting. it is on my zoom at 11am ET: https://umich.zoom.us/my/msaligane
v
Ok sir, Sir, in that meeting I will be able to learn that flow for new design or my error will be solved in that meet sir ?
m
I don't understand what you are trying. So maybe give us an overview?
v
Ok sir Sir, I am trying to build the generator of 4 bit asynchronous up counter using mixed signal Which consist of 3 blocks in which 2 Blocks are analog (ring oscillator and ADC ) AND other block is T flip flop . https://github.com/syedimaduddin/4-bit_Asynchronous_Up_Counter_using_Mixed-Signal I am referring this circuit of which I am trying to make the generator of its combined analog part using dummy verilog code of it's analog block in openFASoC
m
Why are you calling your block AMS if it is a counter
v
Actually, the counter has been made as a mixed signal and I need to generate it's analog part using openFASoc it's a trial design for understanding the flow later on I need to design my own 3 Bit Flash ADC using the same flow
m
What is its analog part?
v
It's ring oscillator and ADC in asynchronous counter design
And in 3 bit flash ADC design the analog part is opamp as a comparator and digital is priority encoder But, first I need to generate the analog part using OPENFASOC for the Counter mixed signal design
Then further /later on will do it for flash ADC
m
Can you show your building blocks schematics
v
Yes sir Please wait let me share it
This is ring oscillator design schematic in xschem
This is opamp as comparator which I have used as ADC
This is .gds file of opamp as comparator generated using ALIGN tool
This is .gds file of Ring oscillator which is also generated using ALIGN tool which is further I need to use as in Input of OpenFASOC FLOW GENERATION