I am using xschem but I don't know how to modify these lines that always get included in my netlist (using ngspice):

What could be the cause for this error which showed while I was performing rte verification for a basic adder. Slack Conversation

What could be the cause for this error which showed while I was performing rte verification for a basic adder.

@Tim Edwards when you get a chance, could you explain how magic handles multiple derivations of the same layer? For example nwell is defined 3 times and pwell twice in the sky130 tech file. nwell

layer nwell NWELL,WELLTXT,WELLPIN
 and-not PNPID
 labels NWELL
 labels WELLPIN port
 labels WELLTXT text
...
 layer nwell pfetarea
 and-not COREID
 grow 180
...
 layer nwell EDID
 and POLY
 and DIFF
 and PSDM
 grow 685
 or ldmos_nwell
 grow 420
 shrink 420

pwell

layer pwell TAP,DIFF
 and-not NWELL,nwelcheck
 grow 130
 or SUBTXT,SUBPIN
 grow 420
 shrink 420
 labels SUBPIN port
 labels SUBTXT text
...
 layer pwell EDID
 and POLY
 and DIFF
 and NSDM
 grow 660
 grow 420
 shrink 420

Hi, I edited a LEF file using Klayout using the sky130A technology and saved it as a GDS. When I open the saved GDS file, the layers are named

1/0

,

1/1

and so on rather than the sky130A names. Loading the layout using the same sky130A technology fails to load the layer properties correct. This does not happen when saved as an OASIS file or MAG layout. Is there some configuration I need to set to correctly save the layout? Thanks.

@Mitch Bailey @Tim Edwards @mehdiour chip has 4 latch-up DRC errors

IO.1a2, IO.1b, IO.3a2, IO.3b

that we've been unable to resolve. These errors manifest in diffusion regions connected to analog IO pads, that has a direct connection between the pad and the drain/source of a transistor. Also, they persist even within the ESD protected Analog IO cells. @Amro Tork do you know anything about this type of errors ? Initially, I attempted to address them by including the

Latchup_MK

mask layer to these diffusion regions, as suggested by 14.3.2 I/O Latch-up Related Rules and Guidelines. They wasn't fixed and, in fact, error

IO.3b

only appeared post the addition of this mask. @Atif Khan @Jorge Marin Has any of the other grups encounter these errors? Link to our GDS file: https://github.com/gabrielmaranhao/Bracolin/blob/main/padframe/RING_PAD_BRACOLIN.gds

sky130_fd_sc_hvl_lsbufhv2lv_1

is showing some DRC errors when I instantiate it (see picture). Complaining about MV diffusion being too close to low-voltage nwell. Anyone come across similar issues with the sky130 hvl library?

Hi @Tim Edwards @Leo Moser Is CACE able to perform operations on GDS? I'm assuming only mag is supported

I don't want do make gate contacts, but klayout makes it automatically. How can I erase them? I can't find the way.

i got this error while run caravel_cocotb -t <file _name> can any one help to resolve it ?