I am doing project Global Foundry 180nm on ASIC tapeout, and the deadline is December 5, 2022. I have a question. I did the MPW precheck, but I cannot pass the tapeout, where I put the MPW precheck pass number and job name as "artificial heart," and it gives me the error "Tapeout for this shuttle is not available at this time." "It will be enabled in the future." Does that mean I'll do it after December 5, 2022? I have attached the images.

Hello I have a rather large digital design that get some XOR errors. I am flattening my design with the user_project_wrapper, so no separate hardening of my design. The XOR errors are on the ports and labels. Some pins look a bit malformed, like one below. Also there is an error in the areaId layer. Are these something to worry about? (The design is magic DRC clean with sky130A. I hit the error with holes in M1 when using sky130B). Thanks!

Hello, I am facing an issue where the standard cell boundaries are altered in the final gds, therefore

area_sc

is off and flow fails with

Diffusion contact to gate < 0.055um (licon.11)

. The boundaries seem to be alright in

results/final/mag/

, but they are altered in

results/final/gds

. The drc-report has multiple entries like

Error while reading cell "(one of the affected sc)" (byte position 126338): Warning: Cell (one of the affected sc) boundary was redefined.

Anyone has seen this before and got an idea what might have happened here? Any help is appreciated Input:

.v

RTL,

.lef

.gds

macrocells (mixed signal)

Hi everyone. Do you know the different between tlef file and lef file?

@Tim Edwards @Tim 'mithro' Ansell @mkk Any idea about the availability date of the SKY90 open-source PDK?

@PramitKumar Pal Did you do what the dialog box says? edit /home/username/.gaw/gawrc and ensure the following line is present and not commented. If not present add it.

up_listenPort = 2020

Also ensure no firewall is blocking local TCP connections on port 2020

Hi i got error regarding the Model i unable to resolve it Please help me screenshot attached could you tell me from when i got colour meaning of wire after simulation @Stefan Schippers @Eric

The shared library isn't found, you can point it before the command with something like:

LD_LIBRARY_PATH=/tools/klayout/bin-release klayout

The new caravel instruction "git clone -b mpw-7a <your github repo URL> caravel_example" is not working.

On a clean working area, after following the steps outlined in the documentation, when I run

make verify-io_ports

, I get the below error.

/<path>/caravel/verilog/rtl/caravel_netlists.v:90: Include file mgmt_core_wrapper.v not found