Hi!
I am trying to add a standard cell DFF in openlane by cell name: sky130_fd_sc_ms__dlrtp_1, but I get this error.
[INFO]: Using configuration in '../home/vboxuser/Documents/GitHub/samj-user-project/openlane/user_proj_example/config.json'...
[INFO]: PDK Root: /home/vboxuser/Documents/GitHub/samj-user-project/dependencies/pdks
[INFO]: Process Design Kit: sky130A
[ERROR]: Standard Cell Library 'sky130_fd_sc_ms' not found in PDK.
make[1]: *** [Makefile:80: user_proj_example] Error 255
make[1]: Leaving directory '/home/vboxuser/Documents/GitHub/samj-user-project/openlane'
make: *** [Makefile:126: user_proj_example] Error 2
user_proj_example.v
`default_nettype none
module user_proj_example (
`ifdef USE_POWER_PINS
inout wire vccd1, // User area 1 1.8V supply
inout wire vssd1, // User area 1 digital ground
`endif
// Wishbone clock input
input wire wb_clk_i,
// Logic Analyzer Signals
input wire la_data_in, // Single bit input
output wire [127:0] la_data_out // 128-bit output, but we only drive the first 2 bits
);
reg la_data_in_delayed_0; // Register for introducing delay
// Introduce delay on la_data_in using an always block
always @(posedge wb_clk_i) begin
la_data_in_delayed_0 <= la_data_in; // Delay la_data_in by one clock cycle
end
/*tiny_test counter(
.clk(wb_clk_i), // Use wb_clk_i as the clock signal
.rst(1'b0), // Hardwire reset to 0 if you don't need a reset signal
.d(la_data_in_delayed), // Input data is la_data_in
.q(la_data_out[0]), // Output q
.qb(la_data_out[1]) // Output qb
);*/
sky130_fd_sc_ms__dlrtp_1 u_sky130_fd_sc_ms__dlrtp_1 (
.D(la_data_in_delayed_0), // Data input
.Q(la_data_out[0]), // True output
.Q_N(la_data_out[1]), // Complementary output
.RESET_B(1'b1), // Reset is inactive (1'b1 for no reset)
.GATE(wb_clk_i) // Gating signal, often connected to the clock
);
// Set remaining bits of la_data_out to high impedance to avoid shorts
assign la_data_out[127:2] = {126{1'bz}};
endmodule
`default_nettype wire
config.json
{
"DESIGN_NAME": "user_proj_example",
"DESIGN_IS_CORE": 0,
"STD_CELL_LIBRARY": "sky130_fd_sc_ms",
"VERILOG_FILES": [
"dir::../../verilog/rtl/defines.v",
"dir::../../verilog/rtl/user_proj_example.v"
],
"CLOCK_PERIOD": 25,
"CLOCK_PORT": "wb_clk_i",
"CLOCK_NET": "counter.clk",
"FP_SIZING": "absolute",
"DIE_AREA": "0 0 2800 880",
"FP_PIN_ORDER_CFG": "dir::pin_order.cfg",
"MAX_TRANSITION_CONSTRAINT": 1.0,
"MAX_FANOUT_CONSTRAINT": 16,
"PL_TARGET_DENSITY": 0.55,
"PL_RESIZER_SETUP_SLACK_MARGIN": 0.4,
"GLB_RESIZER_SETUP_SLACK_MARGIN": 0.2,
"GLB_RESIZER_HOLD_SLACK_MARGIN": 0.2,
"PL_RESIZER_HOLD_SLACK_MARGIN": 0.4,
"MAGIC_DEF_LABELS": 0,
"SYNTH_BUFFERING": 0,
"RUN_HEURISTIC_DIODE_INSERTION": 1,
"HEURISTIC_ANTENNA_THRESHOLD": 110,
"GRT_REPAIR_ANTENNAS": 1,
"VDD_NETS": [
"vccd1"
],
"GND_NETS": [
"vssd1"
],
"IO_SYNC": 0,
"BASE_SDC_FILE": "dir::base_user_proj_example.sdc",
"RUN_CVC": 1,
"pdk::sky130*": {
"FP_CORE_UTIL": 45,
"RT_MAX_LAYER": "met4",
"scl::sky130_fd_sc_hd": {
"CLOCK_PERIOD": 25
},
"scl::sky130_fd_sc_hdll": {
"CLOCK_PERIOD": 10
},
"scl::sky130_fd_sc_hs": {
"CLOCK_PERIOD": 8
},
"scl::sky130_fd_sc_ls": {
"CLOCK_PERIOD": 10,
"SYNTH_MAX_FANOUT": 5
},
"scl::sky130_fd_sc_ms": {
"CLOCK_PERIOD": 10
}
},
"pdk::sky130*": {
"FP_CORE_UTIL": 45,
"RT_MAX_LAYER": "met4",
"scl::sky130_fd_sc_ms": {
"CLOCK_PERIOD": 10
}
},
"pdk::gf180mcuC": {
"STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu7t5v0",
"CLOCK_PERIOD": 24.0,
"FP_CORE_UTIL": 40,
"RT_MAX_LAYER": "Metal4",
"SYNTH_MAX_FANOUT": 4,
"PL_TARGET_DENSITY": 0.45
}
}
Is there any other way to add STD CELL LIBRARY.
