Has anyone done gatelevel netlist simulations with the verilog output from OpenLANE? I've been trying to get it working without any sucess using Icarus Verilog. Specifically, openLane instantiates flip-flops using the
sky130_fd_sc_hd__dfxtp
module, which then instantiates the primitive
sky130_fd_sc_hd__udp_dff$P_pp$PG$N
but doesn't actually make any connections between the two, meaning the simulation doesn't work.
Trying a very simple 11-primitive netlist, the schematic openLane generates seems good, having sketched it out and followed the logic through manually - it just doesn't seem to be simulateable.
Specifically, using the install of SKY130 that came with OpenLane, my design instantiates several D flops, so I pointed icarus at the gatelevel netlist and these two files:
sky130A/libfs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v
and
sky130A/libfs.ref/sky130_fd_sc_hd/verilog/primitives.v
. My netlist then instantiates this flop:
module sky130_fd_sc_hd__dfxtp (
Q ,
CLK,
D
);
// Module ports
output Q ;
input CLK;
input D ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire CLK_delayed;
wire awake ;
// Name Output Other arguments
sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
buf buf0 (Q , buf_Q );
endmodule
You can see the issue here - unless I'm misunderstanding the verilog, the wire
CLK_delayed
is left unconnected, so the primitive which actually handles the logic never sees any input (and icarus bears this out -
CLK_delayed
is simulated as constant
x
).
Is this the correct way to be doing simulations, or sky130 not suitable for simulations, or is this an actual bug I've found?
