Tim Edwards
02/12/2021, 3:44 PMStefan Schippers
02/12/2021, 5:00 PM~/.xschem/simulations/schematic_name.spice
If you press Shift-A
in the schematic window you enable displaying a dialog with the netlist file in it after pressing the '`Netlist`' button.
If this does not happen then there is an installation problem. Let me know if this is the case.
Default location of created netlist files can be changed in xschemrc: set netlist_dir <path>
, or by menu Simulation->Set Netlist dir
if xschem is invoked to create a netlist in batch mode the netlist path is specified with xschem .... --netlist_path <path>
.
Default name of netlist is the name of the schematic with .spice appended.
File name of netlist can be changed in command-line mode with --netlist_filename <file>
as well as with Simulation menu.Tim Edwards
02/13/2021, 2:38 AMTim Edwards
02/13/2021, 10:26 PMStefan Schippers
02/13/2021, 11:07 PMTim Edwards
02/16/2021, 10:33 PMStefan Schippers
02/17/2021, 9:54 AMVarun Majji
02/17/2021, 4:10 PMVarun Majji
02/18/2021, 2:51 PMStefan Schippers
02/18/2021, 3:13 PMVarun Majji
02/20/2021, 7:47 AMStefan Schippers
02/20/2021, 11:03 PMSurag P
02/23/2021, 11:14 AMTim Edwards
02/23/2021, 1:30 PMSurag P
02/25/2021, 11:55 AMWeston Braun
02/28/2021, 10:16 AMStefan Schippers
02/28/2021, 11:17 PM.save all
in the simulator commands.Weston Braun
03/02/2021, 2:33 AMWeston Braun
03/02/2021, 2:33 AMWeston Braun
03/02/2021, 3:00 AMwbraun@wbraun-desktop:~/projects/sky130-analog/designs/ringosc$ netgen -batch lvs "layout/lvs.spice ringosc_flat" "/home/wbraun/.xschem/simulations/ringosc_subcircuit_lvs.spice ringosc_subcircuit" $PDKPATH/libs.tech/netgen/sky130A_setup.tcl
Netgen 1.5.168 compiled on Sat 27 Feb 2021 12:04:34 AM PST
Warning: netgen command 'format' use fully-qualified name '::netgen::format'
Warning: netgen command 'global' use fully-qualified name '::netgen::global'
Reading netlist file layout/lvs.spice
Call to undefined subcircuit sky130_fd_pr__pfet_01v8_hvt
Creating placeholder cell definition.
Call to undefined subcircuit sky130_fd_pr__nfet_01v8
Creating placeholder cell definition.
Reading netlist file /home/wbraun/.xschem/simulations/ringosc_subcircuit_lvs.spice
Call to undefined subcircuit sky130_fd_sc_hd__inv_1
Creating placeholder cell definition.
Reading setup file /usr/share/pdk/sky130A/libs.tech/netgen/sky130A_setup.tcl
Model sky130_fd_pr__nfet_01v8 pin 1 == 3
No property mult found for device sky130_fd_pr__nfet_01v8
No property sa found for device sky130_fd_pr__nfet_01v8
No property sb found for device sky130_fd_pr__nfet_01v8
No property sd found for device sky130_fd_pr__nfet_01v8
No property nf found for device sky130_fd_pr__nfet_01v8
No property nrd found for device sky130_fd_pr__nfet_01v8
No property nrs found for device sky130_fd_pr__nfet_01v8
Model sky130_fd_pr__pfet_01v8_hvt pin 1 == 3
No property mult found for device sky130_fd_pr__pfet_01v8_hvt
No property sa found for device sky130_fd_pr__pfet_01v8_hvt
No property sb found for device sky130_fd_pr__pfet_01v8_hvt
No property sd found for device sky130_fd_pr__pfet_01v8_hvt
No property nf found for device sky130_fd_pr__pfet_01v8_hvt
No property nrd found for device sky130_fd_pr__pfet_01v8_hvt
No property nrs found for device sky130_fd_pr__pfet_01v8_hvt
Comparison output logged to file comp.out
Logging to file "comp.out" enabled
Contents of circuit 1: Circuit: 'ringosc_flat'
Circuit ringosc_flat contains 14 device instances.
Class: sky130_fd_pr__nfet_01v8 instances: 7
Class: sky130_fd_pr__pfet_01v8_hvt instances: 7
Circuit contains 9 nets.
Contents of circuit 2: Circuit: 'ringosc_subcircuit'
Circuit ringosc_subcircuit contains 7 device instances.
Class: sky130_fd_sc_hd__inv_1 instances: 7
Circuit contains 9 nets.
Circuit 1 contains 14 devices, Circuit 2 contains 7 devices. *** MISMATCH ***
Circuit 1 contains 9 nets, Circuit 2 contains 9 nets.
Result: The top level cell failed pin matching.
Logging to file "comp.out" disabled
LVS Done.
yrrapt
03/02/2021, 6:53 AMTim Edwards
03/02/2021, 2:05 PMA.spice
subcircuit A
against a schematic-captured netlist B.spice
subcircuit B
. But B.spice
is just a subcircircuit, and to simulate it you have to include library files B1.spice
and B2.spice
which are not in the netlist file. Then you can create a script my_lvs.tcl
to pass to netgen that looks like this:
set file1 [readnet A.spice]
set file2 [readnet B.spice]
readnet B1.spice $file2
readnet B2.spice $file2
lvs "$file1 A" "$file2 B" sky130A_setup.tcl comp.out
Then run netgen -batch my_lvs.tcl
to run LVS.Stefan Schippers
03/02/2021, 5:00 PM.include
lines (usually done using code*.sym
symbols in xschem) can be placed at lower level hierarchies (thus not only in the testbench). Adding a '`only_toplevel=true`' in these code blocks the content will be dumped to netlist only if netlisting the schematic as a toplevel. If netlisting a testbench instantiating a symbol of the schematic containing said code block this will be totally skipped if '`only_toplevel=true`' attribute is present.
Another useful switch is in Simulation->LVS netlist: top level is a subckt
. This will wrap the top level schematic in a .subckt ... .ends declaration. Some LVS tools need that.Weston Braun
03/02/2021, 8:09 PMWeston Braun
03/02/2021, 8:20 PMWeston Braun
03/02/2021, 8:21 PMWeston Braun
03/02/2021, 8:28 PMTim Edwards
03/02/2021, 10:45 PMWeston Braun
03/02/2021, 11:23 PMWeston Braun
03/02/2021, 11:24 PM