open-source-silicon #verilog-learners

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Ram

12/25/2021, 4:52 PM

set the channel description: practicing verilog #RTL#TestBench

Ram

12/25/2021, 5:16 PM

@User has left the channel

Josuah Demangeon

07/11/2022, 7:35 AM

learning verilog means a lot of troubleshooting of the toolchain

Josuah Demangeon

07/11/2022, 7:35 AM

yosys gives great support for verilog though, mostly the systemverilog veatures are at pain

Josuah Demangeon

07/11/2022, 7:36 AM

in case you use a yosys/verilator (or other simulation tool)

Josuah Demangeon

07/11/2022, 7:36 AM

I would advise to run verilator first to check for correctness of the verilog source

Josuah Demangeon

07/11/2022, 7:36 AM

and then, not consider that everything work, but also check the yosys tool for support of everything

Josuah Demangeon

07/11/2022, 7:37 AM

the warning are not always to ignore, they sometimes tell "we did not know what to do with that, so we did let that unplugged and kept going"

Josuah Demangeon

07/11/2022, 7:38 AM

in case there are difference between simulation and in-fpga, this could come from the difference of features supported

Josuah Demangeon

07/11/2022, 7:38 AM

which is kind of scary for ASICs, since it is not like you can reflash your ASIC every five minute to debug your toolchain :D

Steven Kiss

07/12/2022, 2:25 PM

@Steven Kiss has left the channel