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Hi, Could anyone please tell why I am getting so much large delay for the highlighted cell in the below attached timing report? It is occurring in the reset path of flops. If it is due to high fanout then how I can handle this issue? I have synthesized the design in Openlane using yosys and performed STA using openSTA. The version of Openlane is RC5 and the PDK is Skywater 130 A. The library is "sky130_fd_sc_hd__tt_025C_1v80.lib". Thanking you in anticipation

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People here might be interested in a recent presentation that Antmicro did at the ESSCIRC workshop about "Pre-silicon testing of SkyWater MPW designs using co-simulation with Renode and Verilator" found @ https://docs.google.com/presentation/d/e/2PACX-1vT2pOMi-crvIhns7ulGvmvDdFy7pGb0L28kJouSnseVHl4fHugabSz5yLD5ocU7CfaTtNVSWDyJwl9b/pub?start=false&loop=false&delayms=3000

@Philipp Gühring Try https://docs.google.com/presentation/d/e/2PACX-1vT8OYu5lkpaHLJeBu07BFR-3u88vtRHOnKsIBAVSk4gLCa3-GaDWUny1XQ_rEJxaMJgl6LbmtbBXayc/pub?start=false&loop=false&delayms=3000

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