Will have to fix that

Which one?

The only one I know about is the above toy-sram repo which didn't turn up in any Google searches I just did

Cool - will fix

@User Did you share https://github.com/google/skywater-pdk-libs-sky130_fd_bd_sram and https://raw.githubusercontent.com/google/skywater-pdk-libs-sky130_fd_bd_sram/main/docs/build-space-layout.svg ?

Yes

It would be great if the slides from the OpenPower Summit were published somewhere too

the repo should be mirrored to github and gitlab soon

no one will ever find them where they are now 😀

i think the slides are basically from items in the doc folder. will put out the presentation ones one i get them.

BTW It might be of interested to you that Andrew Zonenberg has finally started doing characterization of the first OpenRAM test IC we did. This was the original 3 designs done back before we launched the MPW program. The testing had been delayed primarily due to part supply issues on the testing hardware (but Andrew also did have a new baby). Andrew is tweeting publically about this results here --> https://twitter.com/azonenberg/status/1462620420113240064

thanks, that's good to know.

s8_dp_sram.gds s8_dp_sram.pdf s8_sp_sram.gds s8_sp_sram.pdf

oh i was just gonna ask if you got in. good!

looking at test_ra_sdr.vcd. i think this is from test_ra_sdr.sv. is this the right test? appears to be some array i/o activity but not what is intended(?)

@Abhishek Das @James Stine i converted the original pyverilator test to cocotb/icarus. there is an fst wavefile here to check for expected array behavior (64x72 sdr logical array)... https://git.openpower.foundation/cores/toy-sram/src/branch/master/rtl/sim/coco

cool!

we got a layout today - we are just testing to see if its okay and we can start generating an array

the mpw repo is here: https://github.com/OpenPOWERFoundation/toy-sram-mpw7

there are some rtl updates there to allow component selection

updated mpw repo. was able to get to clocks/reset with dv test toysram_scan. but looks like vexriscv runs some ops but is hung on an ifetch with no ack.

updated repo. vexriscv now boots to completion and toysram_scan test is working.

updated repo. vexriscv starting to talk to toysram site over wb. but it's going wonky after a bit.

@James Stine @Abhishek Das @Ryan Ridley updated repo. got two site tests running: i/o scan/array access, wb write/read

cool

@James Stine Looks like the tapeout is 9-11; thought it was 9-18. When do you expect to have the gds, etc. to try to build site?