Matt Venn
08/29/2022, 9:12 PMMatt Venn
08/29/2022, 9:13 PMtnt
08/29/2022, 9:15 PMdfxtn
😕tnt
08/29/2022, 10:02 PMTom Spyrou
08/29/2022, 10:46 PMtnt
08/29/2022, 10:56 PMMatt Venn
08/30/2022, 11:03 AMMatt Venn
08/30/2022, 11:04 AMtnt
08/30/2022, 1:03 PMsub[N-1:0]
with a_in
/ b_in
input ports and a_out
/ b_out
output ports and they're all chained a[N-1:0]
an b[N-1:0]
. Is there a way to write a SDC so that the delay from a_out
to the next block a_in
and the delay from b_out
to the next block b_in
are within some margin of each other ?tnt
08/30/2022, 1:06 PMset_bus_skew
maybe.Tom Spyrou
08/30/2022, 6:02 PMtnt
08/30/2022, 6:16 PMTom Spyrou
08/30/2022, 7:37 PMTom Spyrou
08/30/2022, 7:40 PMTom Spyrou
08/30/2022, 7:40 PMTom Spyrou
08/30/2022, 7:41 PMtnt
08/30/2022, 9:35 PMTim Edwards
08/31/2022, 1:05 AMTom Spyrou
08/31/2022, 1:23 AMRyan R
08/31/2022, 7:17 AMMatt Venn
08/31/2022, 9:00 AMMatt Venn
08/31/2022, 9:00 AMMatt Venn
08/31/2022, 9:04 AMTobias Strauch
08/31/2022, 9:22 AMtnt
08/31/2022, 11:45 AMtnt
08/31/2022, 11:45 AMtnt
08/31/2022, 11:45 AMMatt Venn
08/31/2022, 11:57 AMTobias Strauch
08/31/2022, 12:24 PMtnt
08/31/2022, 12:28 PM