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#system-verilog-learners
  • r

    Ram

    12/25/2021, 4:57 PM
    set the channel description: SV_Learners from scratch to advance
  • h

    Hanssel Enrique Morales Norato

    06/27/2022, 6:28 PM
    Is there any open source tool for system verilog simulation?
    a
    • 2
    • 1
  • j

    Josuah Demangeon

    07/05/2022, 10:07 AM
    hello SystemVerilog documentation scavengers
  • j

    Josuah Demangeon

    07/05/2022, 10:08 AM
    I am currently discovering the interface/endinterface feature, which helps a lot with these large set of bus connections signals
  • j

    Josuah Demangeon

    07/05/2022, 10:09 AM
    there seem to be lacking support for them for quite a few open-source tools
  • j

    Josuah Demangeon

    07/05/2022, 10:10 AM
    in case anyone has an example of interfaces being used in synthesis with the yosys or verilator or icarus verilog tools, it would help
  • j

    Josuah Demangeon

    07/05/2022, 10:11 AM
    if at the opposite, you would like to try grouping your numerous signals passed from module to module in interfaces, I may help
  • j

    Josuah Demangeon

    07/05/2022, 10:11 AM
    eventually, I'd have figured by the time
  • j

    Josuah Demangeon

    07/05/2022, 10:15 AM
    the various LowRISC teams (ibex, opentitan...) came upon the consensus to not use them because one of their tool did not support them in 2018, which might have blocked the whole toolchain
  • j

    Josuah Demangeon

    07/05/2022, 10:16 AM
    hopefully 4 years later it is reasonable to give it another go
  • j

    Josuah Demangeon

    07/05/2022, 10:22 AM
  • j

    Josuah Demangeon

    07/05/2022, 10:45 AM
    I got luckier than I thoguht. With help of that example I could try something on my end.
  • j

    Josuah Demangeon

    07/05/2022, 10:46 AM
    and the solution to at least check the correct use of interfaces was upgrading verilator to 4.x. Very easy to compile (even on OpenBSD! no patch needed) and much better support and linting
  • j

    Josuah Demangeon

    07/05/2022, 10:54 PM
    one interesting point here: Verilator supports SystemVerilog interfaces and modport, and through them, it could warn me of a clock domain crossing issue
  • j

    Josuah Demangeon

    07/05/2022, 10:55 PM
    I had the source and direction inverted, and it could find it
    👍 1