open-source-silicon #swerv

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verification-be

s

Srini Vemuri

12/07/2020, 9:28 PM

the skywater pdk github libraries directory is what i am scanning..??

s

Srini Vemuri

12/07/2020, 9:28 PM

https://github.com/google/skywater-pdk

s

Srini Vemuri

12/07/2020, 9:29 PM

OK thanks!

s

Srini Vemuri

12/08/2020, 4:01 PM

hi guys.. we have the std cells... but the DFFRAM library is not in the kit we downloaded... is it a different location?

m

mkk

12/08/2020, 5:06 PM

@User??

m

mshalan

12/08/2020, 5:07 PM

The DFFRAM can be found @ https://github.com/shalan/DFFRAM

s

Srini Vemuri

12/08/2020, 5:25 PM

thanks Mohamed... do you know if we have to do anything specific for test access etc.? for scan or bist?

s

Srini Vemuri

12/08/2020, 5:26 PM

if we give you Synthesis netlist without any scan or bist in it... do you have the flow that inserts the chains and bist logic?

s

Srini Vemuri

12/08/2020, 6:33 PM

also, another quick question. do you have the memory map config that you's like to use for the SOC

s

Srini Vemuri

12/08/2020, 6:34 PM

we need to build and syntheisze for that config.. we can use the same as what you tried for EH1

m

mshalan

12/08/2020, 9:01 PM

@User please check my other project for scan insertion and ATPG: https://github.com/Cloud-V/Fault

m

mshalan

12/08/2020, 9:04 PM

@User Regarding the SoC configuration, any configuration that fits the available area and i/o pads is good enough

s

Srini Vemuri

12/09/2020, 4:10 PM

Hi Mohamed,

s

Srini Vemuri

12/09/2020, 4:11 PM

Can we have a quick meeting so we are in Sync. I am available today as long as we are able to catch each other. You can call on by mobile. 6102975573.

s

Srini Vemuri

12/09/2020, 4:11 PM

that is a US number so +1..

s

Srini Vemuri

12/09/2020, 4:12 PM

I was more interested int he memory addressing map for the SOC.

m

mshalan

12/09/2020, 5:45 PM

@User yes. Are you available now for a zoom meeting?

s

Srini Vemuri

12/09/2020, 6:19 PM

yes.. I am

m

mshalan

12/09/2020, 6:21 PM

I have 10 mins till my next meeting

s

Srini Vemuri

12/09/2020, 6:56 PM

Good catching up.. thanks for your time..

m

mkk

12/10/2020, 6:35 PM

@User @User check

m

mkk

12/11/2020, 5:29 PM

@User could you fork this https://github.com/efabless/caravel repo under the CHIPS Alliance https://github.com/chipsalliance

m

mkk

12/11/2020, 5:30 PM

then change the name top caravel-swerv-el2 ---> https://github.com/chipsalliance/caravel-swerv-el2

m

mkk

12/11/2020, 5:30 PM

and make it public

s

Srini Vemuri

12/11/2020, 5:42 PM

got it!

m

mkk

12/11/2020, 5:44 PM

@User thank you 🙏

s

Srini Vemuri

12/12/2020, 1:45 AM

just uploaded the https://github.com/chipsalliance/caravel-swerv-el2/blob/master/verilog/gl/el2_swerv_wrapper.v

s

Srini Vemuri

12/12/2020, 1:46 AM

I will send some integration notes to Prof. Shalan in an email.

m

mkk

12/13/2020, 4:04 PM

@User @User I think we need to have a call asap

t

Tim Edwards

12/12/2022, 2:04 PM

@Tim Edwards has left the channel