@User docs for xschem, magic, ngspice and open_pdks (the skywater-pdk stuff). On opencircuitdesign.com you'll find good info for other tools.

while installing pdks this is showing from 10 minutes is it normal ?? Posted in #general

Hi everyone, I have synthesized my design in Vivado, the design uses 22000 LUT and 15000 flip-flops. Is there a way to estimate if this design fits into caravel user area and how much area it uses?

Hello, I am trying to synthesize my design using openlane, and I get an error in placement. In the picture you can see the log: "12-opendp.log". I am new to physical design, so I honestly I am clueless as what is the problem.

Open source silicon office hours with me & @User tomorrow 18th March at 17:00 CET / 09:00 PT / 21:30 IST Last time we had 20 people join over the hour and ask 17 questions. 12 were answered on the call and the other 5 were solved during the week. Questions and Answers are on the google doc: https://docs.google.com/document/d/1BbkCsNwfJkvmScaUGP30GDEIam9dG75RE6M9uHJqpZc/edit#heading=h.ylb1q0qgcruk Hope to see you there! Video call link: https://meet.google.com/rkw-qhhq-qkx

While importing reram layout in magic only metal1, metal2 and via are found available. are BE and TE terminals metal1 and metal 2 respectively? Also I get a distorted view of reram cell layout with labels of the terminals overlapped (thick blue area). How can I remove it? Also how will I create a copy of a cell in magic? any help.

public office hours starting in 5 minutes! https://docs.google.com/document/d/1BbkCsNwfJkvmScaUGP30GDEIam9dG75RE6M9uHJqpZc/edit# Video call link: https://meet.google.com/oja-gwjj-hsa

Hi there!! also drawing attention @User Sir, I am a newbie in this group and better to say I'm new to IC design by open source tools. So recently I started to integrate Linux ubuntu on my VMware and then followed this tutorials https://www.udemy.com/course/vsd-a-complete-guide-to-install-open-source-eda-tools/ and successfully done everything but then followed https://www.udemy.com/course/vsd-a-complete-guide-to-install-openlane-and-sky130nm-pdk/ and i have done everything but in the last video I could not pull the docker as instructor also could not at first couple of attempt but then he did restart the system and said it worked this time which I did but for me did not work. Here I am attaching the screen shot of my terminal Apart from this, I would like to get help on how to start designing IC by all these open source tools? Some links or suggestions carrying complete guideline On IC design flow is what I needed. T.I.A.

Hi Post-floorplan reports says that the design has initial fp core area : 5.52 10.88 1900.26 1904.0 and initial fp die area: 0.0 0.0 1906.165 1916.885. I'm not sure whether the design fits the caravel user area. Does it or should I find a way to make it fit?

Hello, for the MPW5 I see projects where people disable fill and tapcell insertion at the config.tcl of user_project_wrapper. From the general ASIC tapeout perspective I think that there should be no empty area, it should be filled with filler cells. Am I wrong? Also I want to put buffers on the top level to overcome slew violations at the top level. To integrate them, should I also include tapcells? Maybe the standard cells have taps inside at this technology?

Hello everyone, I came across this problem while trying to harden my design with openlane, could someone please help me to solve it?

We will have one last office hours before tapeout. Monday 21st at 16:00 CET / 20:30 IST / 08:00 PT Last calls questions and answers: https://docs.google.com/document/d/1BbkCsNwfJkvmScaUGP30GDEIam9dG75RE6M9uHJqpZc/edit Video call link: https://meet.google.com/ysg-wivf-cvy

I'm using sky130 SRAM already hardened macro in my design but it is giving DRC violations, can someone suggests how to deal with them?

While running MPW Precheck I'm getting SPDX compliance failed although I have added License header to all rtl files. Anyone knows the reasons and how to avoid it?

Hi. I am trying to create labs on cdc using skye130 libs. Is there a synchronizer cell in the libs? Also any work has been done characterising and identifying parameters like Tau for MTBF calculations?

After opening the layout of empty wrapper in magic, how will i import standard cell layout inside the wrapper? I have tried 'place instance' option. But it doesnt seem to work. Any help? Also grid option is not working after loading the empty wrapper. Is there any way to apply grid after loading the wrapper?

office hours starting now! https://meet.google.com/ysg-wivf-cvy

Minimum which version of centos or required to install sky130

?

I have centos 6.9

how to remove Klayout feol check failed in mpw precheck?

For SKYWATER_MODEL we need to give sky130/libs.tech And For SKYWATER_STDCELLS we need to give sky130/libs.ref Is it right? @User

Note: No compatibility mode selected! Circuit: ** sch_path: /home/manohar/untitled.sch Error: unknown subckt: xm1 net1 net2 0 0 sky130_fd_pr__nfet_01v8 0.15 {1*nf=1 ad=()int((nf+1)/2)} 1.0 0 {()int((nf+2)/2)}} {()2*int((nf+1)/2)}} {()2*int((nf+2)/2)}} {()0.29}} {()0.29}} 0 0 0 1 1 Simulation interrupted due to error! ngspice 11 -> edit untitled.spice ^[ Note: No compatibility mode selected! Circuit: ** sch_path: /home/manohar/untitled.sch Error: unknown subckt: xm1 net1 net2 0 0 sky130_fd_pr__nfet_01v8 0.15 {1*nf=1 ad=()int((nf+1)/2)} 1.0 0 {()int((nf+2)/2)}} {()2*int((nf+1)/2)}} {()2*int((nf+2)/2)}} {()0.29}} {()0.29}} 0 0 0 1 1 run circuit? n running circuit Error: there aren't any circuits loaded.

I get the reram cell as below in magic. What is the blue area in the layout?

Hi Everyone

Hope you are doing well. I was installing skywater 130 nm pdks using the commands on the webpage http://www.opencircuitdesign.com/open_pdks/ I encountered an error while performing the "make" step. There is a screenshot attached to the email which shows the error(s). I am attaching the log files also in order to make you aware of the problem well. It will really be a great help if I reach the solution through your instructions. Thanks in advance.

installskywaterpdk.png,sky130A_make.log,sky130B_make.log

Hi, Hope you are doing well. I have installed xschem zip document on my laptop windows 10 and it's working. However I could'nt download xschem_skywater pdk to use it with xschem. Is there any solution to was this. Thanks in advance.

@User to use xschem with skywater i think you should use a Linux virtual machine may be using Windows Subsystem for Linux (WSL) or other virtualization software (like VirtualBox). Then in the ubuntu machine you install xschem, ngspice and open_pdks, using git, and compiling the source files.

Thanks Mr stefan.