so I believe the SKY130 std cells have a FA/HA in them

most constraint-driven multipliers/adders tend to not use these cells in my experience

but it varies

@User, @User there are various full-adder / half adder cells in skywater-pdk standard cells, at least, i see them in the high-density lib

sky130_fd_sc_hd

Whether synthesis uses them or not (for example yosys) i don't know, need to test :-)

Thx @User saw the HA and FA - yes, my experience show that it depends on constraints, loading and HDL/circuit whethrr its used. I just dont know if yosys supports + and * like Genus and DC. As I said before, within many of my high speed designs I typically see gates other than FA and HA cells. Again it varies but yes SKY130 cells have HA and FA in them. We hope to add a FA and HA cell to OSUs library soon.

@User, @User: yosys does not use cells like FA and HA by default. However, it has methods by which any of its intermediate form structures can be given a specific implementation and mapping. There are a number of such mappings in Openlane; see, e.g.,

open_pdks/sky130/openlane/sky130_fd_sc_hd/fa_map.v

. It is only necessary to read these verilog files into yosys before synthesis.

@User Thanks, this makes very sense. In my experience pure logic synthesis can't do any better than a specialized adder macro (for example blocks of 4 bit carry look ahead adders). I played in the past with yosys trying to get a 256 bit adder and results were always between the worst (ripple carry) and better (CLA) implementations.

@User @User I think we are talking about oranges and apples here. Synthesis is well known in what it does and how it maps intermediate nodes. I am not familiar with the internals of yosys but Tim Edwards is probably right. @User you should check our prefix adder generators https://github.com/tdene/synth_opt_adders. I don't particularly agree with your comment that synthesis cannot do better. DC and Genus do a very nice job with syntax such as a+b or a*b. Yosys is a completely different matter but a very interesting one research wise.

There is wonderful discussion on this within the SIS synthesis tool which predates yosys: Its a great read @User if you are interested: https://www2.eecs.berkeley.edu/Pubs/TechRpts/1992/2010.html

Static Timing Analysis workshop using OpenSTA/Sky130 There is a huge difference between what people think about STA and what STA really is. There is a huge gap in how Physical Designers (including myself) look at STA and how STA engineers look at it. There are many STA performance metrics which Physical designers miss out on, and missed one's are sometimes a major factor for chip failure. I have experienced this first-hand. Irrespective of what your profile is (student, Physical designer, DFT engineer, RTL designer, Professor), if you wish to be in semiconductor for a long run, you need to look at your chip beyond setup/hold violations, because STA signoff analysis is way beyond standard setup/hold violations. So here's an exclusive STA cloud lab based workshop using OpenSTA and Sky130 PDKs. Registration link and workshop content- https://www.vlsisystemdesign.com/sign-off-timing-analysis-basics-to-advanced/ All the best and happy learning

@User while editing capacitor symbols to show the capacitance value based on W and L, i see the

cap_var_hvt

is not loaded in open_pdks spice models. if you see the file

.../share/pdk/sky130A/libs.tech/ngspice/all.spice

it loads:

.include "../../libs.ref/sky130_fd_pr/spice/sky130_fd_pr__cap_var_lvt.model.spice"

but does not load the

cap_var_hvt

high voltage capacitor, although that file exists in libs.ref (

sky130_fd_pr__cap_var_hvt.model.spice

). May be this capacitor is blacklisted /DNU for some reason? EDIT: Looking at the models these 2 capacitors have the same

tox

, so i believe there is no need to have both. the capacitance per area is indeed almost identical, and the

cap_var_lvt

has lower

vth

so behaves closer to an 'ideal' capacitor at low voltages, better than the

cap_var_hvt

Hi @User. I am trying to use openSTA tool for student labs. I don't see clock gating checks and recovery/removal checks being reported. Can you help? the labs are here https://github.com/vikkisachdeva/openSTA_sta_workshop/tree/master/vlsideepdive_openSTA_labs/lab6 https://github.com/vikkisachdeva/openSTA_sta_workshop/tree/master/vlsideepdive_openSTA_labs/lab7

@User @User I am trying to install specific liberty files sky130_fd_sc_hd__ss_025C_1V80.lib and sky130_fd_sc_hd__ff_025C_1V80.lib for my work as a part of vsd hdp program. Can you kindly guide me on how should I proceed. I already have the pdk install using using openlane build script provided by vsd.

hi, is there a way to convert netlist to .mag file. Also the 'devices' option is not showing up in the magic tool so that Iam unable to import standard cells from skywater pdk?

did you privide the rcfile?

why 'devices' option is missing in magic which prevents me from loading the standard cell layouts available with skywater pdk in magic? any fixes?

I'm getting this error while running make user_proj_example for my custom design. I assume my die area is less than what is required. I set die area 0 0 2000 2000. Can someone tell what are the coordinates to utilize all the user project area? And this error really is due to less die are or due to something else?

Is there a way I can use Cadence/Synopsys tools to generate the GDS for my design instead of the open source tools? If yes, can someone please point me to the right resources/people? Many thanks!

Yes, if you have Cadence licenses, you can follow our labs: https://github.com/EECS150/asic_labs_fa21 (sky130 option), which will generate layout. Lab 6 doesn't have a Sky130 version, because OpenRAM doesn't mix well with other memory macros, we may have some alternatives in a few months. Behind the labs is a tool called Hammer: https://github.com/ucb-bar/hammer/. There is an e-mail alias through which you can ask for non-public plugins for commercial tools.

Detection of well connections is now available for sky130. See #verification-be https://skywater-pdk.slack.com/archives/C017UA7LEUV/p1646886489345219

Hi, where may I find the spice files for cells sky130_fd_pr__cap_mim_m3__base and sky130_fd_pr__cap_mim_m4_base? I see them on https://skywater-pdk.readthedocs.io/en/main/rules/device-details.html#spice-model-information but could only see cap_mim_m3_1 and cap_mim_m3_2 in the repo. Thanks! @User

Hi everyone is there any tutorial to learn about the XSchem skywater 130nm technology. I am a beginner, I don't no much about this programs I cannot even download and install them to my pc. Can someone also provide me the best process on how I can downlaod them. I am a 3rd year Electrical and Elektronics student and I am planning to design 4th order butterworth lowpass filter that has a 2 cutoff frequencies 10Mhz and 20MHz with my Team. Thanks everyone

Tomorrow (Friday) at 17:30 CET I will have an open doors office hours video call. I'll aim to answer questions and help troubleshooting. Asic office hours Friday, 11 Mar • 1730–1830 Google Meet joining info Video call link: https://meet.google.com/ttc-hhfp-cot Posted in #shuttle

ASIC office hours in 20 minutes: https://meet.google.com/ttc-hhfp-cot

how to run openlane interactively in caravel?

where can i find the .mag file of reram cell from skywater pdk? So far what i could find is the .gds file. Any help?

is there any tutorial on how to connect ngspice to sky130 ?

is there a json2liberty command - to reverse json files back to liberty that cadence and synopsis can read?

Could anyone share a link or note file(installation guide) to install skywater pdk, NetGen, ngspice and xscham