Abdul Rawoof Shaik
01/04/2021, 6:54 PMyrrapt
01/04/2021, 7:12 PMtnt
01/04/2021, 7:35 PMyrrapt
01/04/2021, 7:49 PMtnt
01/04/2021, 8:15 PMyrrapt
01/04/2021, 8:30 PMStefan Schippers
01/04/2021, 8:35 PMAbdul Rawoof Shaik
01/04/2021, 11:04 PMAbdul Rawoof Shaik
01/04/2021, 11:23 PMStefan Schippers
01/04/2021, 11:30 PMStefan Schippers
01/04/2021, 11:59 PMStefan Schippers
01/05/2021, 12:09 AMAbdul Rawoof Shaik
01/05/2021, 1:04 AMStefan Schippers
01/05/2021, 2:33 AM.subckt lvtnot a y VCCPIN VSSPIN W_N=1 L_N=0.15 W_P=2 L_P=0.35
XM2 y a VCCPIN VCCPIN sky130_fd_pr__pfet_01v8_lvt L=L_P W=W_P nf=1
XM1 y a VSSPIN VSSPIN sky130_fd_pr__nfet_01v8_lvt L=L_N W=W_N nf=1
.ends
while the inverter with area/perimeters specified is:
.subckt lvtnot a y VCCPIN VSSPIN W_N=1 L_N=0.15 W_P=2 L_P=0.35
*.opin y
*.ipin a
XM2 y a VCCPIN VCCPIN sky130_fd_pr__pfet_01v8_lvt L=L_P W=W_P nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
+ sa=0 sb=0 sd=0 mult=1 m=1
XM1 y a VSSPIN VSSPIN sky130_fd_pr__nfet_01v8_lvt L=L_N W=W_N nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
+ sa=0 sb=0 sd=0 mult=1 m=1
.ends
Tim Edwards
01/05/2021, 3:34 AMStefan Schippers
01/05/2021, 1:53 PM14685 : m.xm2.msky130_fd_pr__nfet_01v8 net2 g net6 net4 xm2:sky130_fd_pr__nfet_01v8__model l= 1.49999999999999994e-01 w= 1.00000000000000000e+00 nf= 1.00000000000000000e+00 ad= 0.00000000000000000e+00 as= 0.00000000000000000e+00 pd= 0.00000000000000000e+00 ps= 0.00000000000000000e+00 nrd= 0.00000000000000000e+00 nrs= 0.00000000000000000e+00 sa= 0.00000000000000000e+00 sb= 0.00000000000000000e+00 sd= 0.00000000000000000e+00 m= 1.00000000000000000e+00
1. However having these parameters set to zero does NOT mean there are no drain/source to substrate junction diodes, diodes clamping forward bias conditions still exists, however the I/V characteristics are different.
2. Transistor with no area/perimeters set has lower substrate leakage, picture in following post
3. the IV characteristic of the Body terminal when forward biased w.r.t source and drain (set at 0V) is strange: at 27C transistor with no area/perimeters set has higher current, while at 150C it has lower current. I do not understand the reason.Stefan Schippers
01/05/2021, 1:57 PMTim Edwards
01/06/2021, 10:04 PMcommit a7915eafb7da936dfca574c792a384db1b060989
will take care of it. The devices in the netlists in the libraries won't get the AD/AS/PD/PS values until the libraries are rebuilt, although I could potentially stop installing the SPICE netlists from the libraries, and have magic regenerate them by extraction as part of the PDK install.Stefan Schippers
01/07/2021, 12:51 AMTim Edwards
01/07/2021, 2:06 AMStefan Schippers
01/07/2021, 2:55 AMTim Edwards
01/07/2021, 3:02 AMTim Edwards
01/07/2021, 3:03 AMStefan Schippers
01/07/2021, 3:12 AMStefan Schippers
01/07/2021, 3:17 AMTim Edwards
01/07/2021, 3:28 AMTim Edwards
01/10/2021, 2:44 AMmkk
mkk
Matt Venn
01/11/2021, 5:12 PM