Matt Venn
12/25/2020, 8:27 PMMatt Venn
12/25/2020, 8:28 PMMatt Venn
12/25/2020, 8:28 PMMatthew Guthaus
12/25/2020, 9:18 PMtnt
12/26/2020, 1:04 PMmet1
to met2
and I get Via1 width < 0.26um (via.1a + 2 * via.4a)
tnt
12/26/2020, 1:05 PMmet1
.tnt
12/26/2020, 5:24 PMhttps://i.imgur.com/yUW3I6v.png▾
tnt
12/26/2020, 5:25 PMTim Edwards
12/26/2020, 7:26 PMtnt
12/26/2020, 7:28 PMhd
standard cell grid.Tim Edwards
12/26/2020, 7:28 PMTim Edwards
12/26/2020, 7:42 PMScott Davidson
12/26/2020, 10:58 PMKunal
12/27/2020, 1:04 PMHongzhi Song
12/28/2020, 11:45 AMMatthew Guthaus
12/28/2020, 3:44 PMStephen
12/29/2020, 7:54 PMmehdi
12/29/2020, 8:49 PMAdrian Freed
12/29/2020, 11:20 PMAdrian Freed
12/29/2020, 11:23 PMAdrian Freed
12/29/2020, 11:24 PMmehdi
12/29/2020, 11:31 PMMatt Venn
12/30/2020, 5:20 PMRoshan Khatri
01/03/2021, 12:35 PMStefan Schippers
01/03/2021, 8:09 PMxschem
, the xschem_sky130
symbol libraries (transistors, devices, standard cells) , install the skywater-pdk
process files, and build the ngspice
simulator from sources. I think this will be useful for new users to bootstrap a working environment for analog design on the skywater pdk with xschem. I hope it helps.Tim Edwards
01/03/2021, 8:20 PMStefan Schippers
01/03/2021, 9:32 PMStefan Schippers
01/03/2021, 11:58 PMAbdul Rawoof Shaik
01/04/2021, 6:43 PMStefan Schippers
01/04/2021, 6:52 PM