set the channel description: Welcome !! This channel support questions and feedback regarding the private shuttle program announced by Efabless.

See the attached flyer. This solution will be publicly announced this Tuesday, May 18.

Please post any questions or feedback you have. You can also message me directly regarding interest in reserving a slot on one of the shuttles - June or October.

$10k for 10mm^2 is really cost competitive for a 130nm process node. Like the free shuttles, are no modifications allowed to IC test harness?

@User has a polly for you!

How would custom packaging for more IO work?

I'd like to see a bulletin board posted where people can build teams to share a single $10K run. Each person gets a small subsection of one design. Efabless doesn't have to be involved, nor should they, to manage the collaboration. One party in the group is the chip lead and does all the coordination with eFabless. I can see a situation where 4 people split 10mm^2 four ways, each pays $2500. This opens up the opportunity to more people.

@User has been doing something like that for the zero-to-asic project.

Is there a way that we could remove the management soc in the private shuttle and just use the pad frame to enable full customization of the whole die area? @User

Is it possible to get bare dies instead of packaged chips? We are interested in using the service to make sensors, which requires the top surface to be completely exposed. We can do our own wire bonding.

Hello will the private shuttle will have the same area available for user as it is available in open shuttle program?

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Hey everyone, I submitted to the last chipignite shuttle called 2206Q on 06/17. However, what I see on the efabless portal is in the attached image. Is this the expected result? I was expecting the "tapeout" phase also to be highlighted like the "submission" phase. Posted in #shuttle

Check the announcements channel. I'm assuming the delays on the MPW runs are going to impact the chipignite runs as well. @jeffdi could you confirm this?

@Katie that is correct. we are still working through the plan to correct the issues and will update as we get new dates.

I'm getting a strange tapeout job error. I have a fairly a large design integrated into the user_analog_project_wrapper. All precheck and tapout checks pass except for the "Klayout Metal Minimum Clear Area Density". The logs show the following layer densities. It's my understanding that these densities represent the % of empty area on each layer. The numbers are significantly smaller than they should be just based on a quick visual inspection (I'm not using even half the available area per layer), and some of the results are even negative which doesn't make sense. Attempting to run the magic metal density check python script returns an error saying the design is less than 700 x 700 um, which is not the case. Could this be an error in the tapeout check?

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