open-source-silicon #piel

No it's a layout-only design, by just placing SKY130 devices in an array, and then wiring them up. (I just took code from the Laygo2 examples folder, and ran it against the Sky130 PDK). Here's the part specific to the layout above!

👍 1

Kennedy Caisley

09/05/2023, 4:44 PM

Copy code

# Create instances.
in0 = tnmos.generate(name="MN0", params={"nf": nf_b, "tie": "S"})
ip0 = tpmos.generate(name="MP0", transform="MX", params={"nf": nf_b, "tie": "S"})
in1 = tnmos.generate(name="MN1", params={"nf": nf_a, "trackswap": True})
ip1 = tpmos.generate(name="MP1", transform="MX", params={"nf": nf_a, "tie": "S"})

# Place instances, array-based placement
dsn.place(grid=pg, inst=[[in0, in1], [ip0, ip1]], mn=[0, 0])

# Create and place wires.
_mn = [<http://r23.mn|r23.mn>(in1.pins["G"])[0], <http://r23.mn|r23.mn>(ip1.pins["G"])[0]]    # A
va0, ra0, va1 = dsn.route(grid=r23, mn=_mn, via_tag=[True, True])
_mn = [<http://r23.mn|r23.mn>(in0.pins["G"])[0], <http://r23.mn|r23.mn>(ip0.pins["G"])[0]]    # B
vb0, rb0, vb1 = dsn.route(grid=r23, mn=_mn, via_tag=[True, True])
_mn = [<http://r12.mn|r12.mn>(in0.pins["D"])[1], <http://r12.mn|r12.mn>(in1.pins["S"])[0]]    # internal
dsn.route(grid=r23, mn=_mn)
_mn = [<http://r12.mn|r12.mn>(ip0.pins["D"])[1], <http://r12.mn|r12.mn>(ip1.pins["D"])[0]]    # output
dsn.route(grid=r23, mn=_mn)
_mn = [<http://r23.mn|r23.mn>(in1.pins["D"])[1], <http://r23.mn|r23.mn>(ip1.pins["D"])[1]]
_, rout0, _ = dsn.route(grid=r23, mn=_mn, via_tag=[True, True])

# Create pins.
pB = dsn.pin(name="B", grid=r23, mn=<http://r23.mn|r23.mn>(rb0))
pA = dsn.pin(name="A", grid=r23, mn=<http://r23.mn|r23.mn>(ra0))
pout0 = dsn.pin(name="O", grid=r23, mn=<http://r23.mn|r23.mn>(rout0))
_mn = [<http://r12.mn|r12.mn>(in0.pins["RAIL"])[0], <http://r12.mn|r12.mn>(in1.pins["RAIL"])[1]]
pvss0 = dsn.pin(name="VSS", grid=r12, mn=_mn)
_mn = [<http://r12.mn|r12.mn>(ip0.pins["RAIL"])[0], <http://r12.mn|r12.mn>(ip1.pins["RAIL"])[1]]
pvdd0 = dsn.pin(name="VDD", grid=r12, mn=_mn)

Dario Quintero

09/05/2023, 4:47 PM

Pretty cool!

Kennedy Caisley

09/05/2023, 4:50 PM

What would be awesome is if we could implement an interface like this into GDSFactory, over the coming year or so. 👍🏻

Kennedy Caisley

09/05/2023, 4:52 PM

I'm going to spend a couple months using this Laygo2 interface first, I think, to learn how the interface behaves. Then if it seems work integrating, I can port all this functionality over to GDSFactory.

Dario Quintero

09/05/2023, 4:52 PM

Yeah that sounds very cool

Dario Quintero

09/05/2023, 4:52 PM

It'd be interesting when you begin converting from hdl21 to this layout

Dario Quintero

09/05/2023, 4:52 PM

In a way it's a kind of schema change

Dario Quintero

09/05/2023, 4:53 PM

Like a netlist composition to layout proto

Kennedy Caisley

09/05/2023, 4:53 PM

In terms of schematic to layout, for example, the

#Create Instances

section could be pulled entirely from a netlist

Dario Quintero

09/05/2023, 4:53 PM

Or even write placement algorithnms

Dario Quintero

09/05/2023, 4:53 PM

Like automatic placement and routing

Dario Quintero

09/05/2023, 4:53 PM

Using the netlist net names

Kennedy Caisley

09/05/2023, 4:53 PM

The

Create wires

and

create pins

could also be inferred from the netlist.

Dario Quintero

09/05/2023, 4:54 PM

very exciting!

Kennedy Caisley

09/05/2023, 4:55 PM

I don't think the routing can be done in just one way automatically, without limiting the flexibility too much. Analog designs, by nature, are pretty variable. There's no such thing as a 'best layout', it varies from block to block

Kennedy Caisley

09/05/2023, 4:55 PM

So there would need to be a way to choose between different pre-made layout strategies, or an escape hatch to opt for a completely manual method of placing and laying out devices. (If none of the presets are good.)

Kennedy Caisley

09/05/2023, 4:56 PM

But definitely we should save the designer from having to declare as size the devices. That's already been specified in a netlist

Dario Quintero

09/05/2023, 4:57 PM

Look forward to seeing what you come up with

Dario Quintero

09/05/2023, 5:29 PM

Yeah this environment stuff is definitely sorted for now! Some exciting stuff coming up of tools cosimulation I think now

Kennedy Caisley

09/07/2023, 7:52 PM

Do you either of you guys know how to use the Hdl21

sim.save()

attribute when running a batch mode simulation, to save a certain node in the circuit? This is the definition of the valid target parameters for it in the Hdl21 source:

Copy code

# Union of "save-able" types
SaveTarget = Union[
    SaveMode,  # A `SaveMode`, e.g. `SaveMode.ALL`, `SaveMode.SELECTED`, or `SaveMode.NONE`.
    Signal,  # A single `Signal`
    List[Signal],  # A list of `Signal`s
    str,  # A signal signale-name
    List[str],  # A list of signal-names
]

I thought I could then just plug in a

h.Signal

defined earlier, like below. (The line with

sim.save(tb.VDS)

)

Copy code

# Create a test bench module
tb = h.sim.tb()

# Create signals in testbench module
tb.VDS = h.Signal()
tb.VGS = h.Signal()
tb.VBS = h.Signal()

# Create testbench devices in testbench module
tb.dut = nch(MosParams(w=0.5, l=0.15, nf=1))(D=tb.VDS, G=tb.VGS, S=tb.VSS, B=tb.VBS)
tb.VDS_src = Vdc(Vdc.Params(dc=str(vds)))(p=tb.VDS, n=tb.VSS)
tb.VGS_src = Vdc(Vdc.Params(dc=str(vgs)))(p=tb.VGS, n=tb.VSS)
tb.VBS_src = Vdc(Vdc.Params(dc=str(vbs)))(p=tb.VBS, n=tb.VSS)

# Create simulation object, wrapped around testbench module
sim = h.sim.Sim(tb=tb)
sim.lib(f"/tools/kits/SKY/sky130A/libs.tech/ngspice/sky130.lib.spice", 'tt')
sim.op()
sim.save(tb.VDS)               # <--- How to probe the tb.VDS signal?
sim.save(SaveMode.SELECTED)

# Setup sim options
sim_options = SimOptions(
    rundir=Path("./scratch"),
    fmt=ResultFormat.SIM_DATA,
    simulator=SupportedSimulators.XYCE,
)

# Run simulation
sim_results = sim.run(sim_options)

But this isn't working:

NotImplementedError: Unimplemented control card signal: "VDS" for <vlsirtools.netlist.spice.XyceNetlister object at 0x7fe4cd1ffb10>

Any ideas?

Kennedy Caisley

09/07/2023, 7:59 PM

I know that I can also fetch information from the

sim_results

return value from starting

sim.run()

, but I was hoping to learn how to use the

sim.save(...)

approach so that I can produce netlists directly with corresponding

.SAVE

control statements in them. Here's a snippet from the

ngspice

docs about the statements:

Kennedy Caisley

09/07/2023, 8:00 PM

image.png

Thomas Pluck

09/07/2023, 11:02 PM

Xyce AFAIK has had a lot of integration issues with VlsirTools and isn't as well supported as NgSpice, so even ordinary stuff is pretty broken. I find for Sims that

hdl21/sim/data.py

makes for the best documentation, line 292 has the

Save

simattr

definition which will take any

SaveTarget

object which can be lists of Signal name strings or just the Signals themselves (presumably accessed as attributes of the Sim

Tb Module

?).

Thomas Pluck

09/07/2023, 11:05 PM

I just realized, there isn't an actual Hdl21 slack channel is there?

Dario Quintero

09/22/2023, 11:00 AM

I love this apptainer thing, banging recommendation Kennedy! Needed it to setup the nix evironment in centos and it's going well

Kennedy Caisley

09/22/2023, 1:32 PM

Ah, okay that's great that you like it! And how has the nix environment been working? Did you end up adding anything to it?

Dario Quintero

09/22/2023, 2:49 PM

Yeah thanks for that. nix has been good for me, but when we set it up in my collagues different computer, we began running into a few

libstdc++.so.6

c compilation files missing issues and some tkinter import issues too. Has been a bit weird as its only a few machines that have it. We've been trying to sort it out, but currently setting it up in an apptainer server to host the nix setup and then for sure it should be reproducible even in centos or ubuntu