#596 Cannot generate pdn for my design Issue closed by donn The-OpenROAD-Project/OpenLane

Hi! Is this OK, that flow steps in flow_summary.log have [ERROR] messages, but in the final string I have [SUCCESS]: Flow Complited Without Fatal Errors? [INFO]: Running Magic DRC... [INFO]: current step index: 32 [INFO]: Converting Magic DRC Violations to Magic Readable Format... [INFO]: Converting Magic DRC Violations to Klayout XML Database... [INFO]: Converting DRC Violations to RDB Format... [INFO]: Converted DRC Violations to RDB Format [ERROR]: There are violations in the design after Magic DRC. [ERROR]: Total Number of violations is 3872 [INFO]: Calculating Runtime From the Start... [INFO]: Flow failed for ram_dp_bist/08-09_10-54 in 1h59m54s [INFO]: Generating Final Summary Report... [INFO]: Design Name: ram_dp_bist Run Directory: /openLANE_flow/designs/ram_dp_bist/runs/1600x1000 ---------------------------------------- Magic DRC Summary: Source: /openLANE_flow/designs/ram_dp_bist/runs/1600x1000/reports/magic//32-magic.drc Violation Message "P-diff distance to N-tap must be < 15.0um (LU.3) "found 1938 Times. Violation Message "N-diff distance to P-tap must be < 15.0um (LU.2) "found 1934 Times. Total Magic DRC violations is 3872 ---------------------------------------- LVS Summary: Source: /openLANE_flow/designs/ram_dp_bist/runs/1600x1000/results/lvs/ram_dp_bist.lvs_parsed.lef.log LVS reports no net, device, pin, or property mismatches. Total errors = 0 ---------------------------------------- Antenna Summary: No antenna report found. [INFO]: check full report here: /openLANE_flow/designs/ram_dp_bist/runs/1600x1000/reports/final_summary_report.csv [INFO]: Saving Runtime Environment [ERROR]: Flow Failed. [INFO]: Running Antenna Checks... [INFO]: Running OpenROAD Antenna Rule Checker... [INFO]: current step index: 33 [INFO]: current step index: 34 [INFO]: Running CVC [INFO]: current step index: 35 [INFO]: Calculating Runtime From the Start... [INFO]: Flow completed for ram_dp_bist/08-09_10-54 in 2h0m12s [INFO]: Generating Final Summary Report... [INFO]: Design Name: ram_dp_bist Run Directory: /openLANE_flow/designs/ram_dp_bist/runs/1600x1000 ---------------------------------------- Magic DRC Summary: Source: /openLANE_flow/designs/ram_dp_bist/runs/1600x1000/reports/magic//32-magic.drc Violation Message "P-diff distance to N-tap must be < 15.0um (LU.3) "found 1938 Times. Violation Message "N-diff distance to P-tap must be < 15.0um (LU.2) "found 1934 Times. Total Magic DRC violations is 3872 ---------------------------------------- LVS Summary: Source: /openLANE_flow/designs/ram_dp_bist/runs/1600x1000/results/lvs/ram_dp_bist.lvs_parsed.lef.log LVS reports no net, device, pin, or property mismatches. Total errors = 0 ---------------------------------------- Antenna Summary: Source: /openLANE_flow/designs/ram_dp_bist/runs/1600x1000/reports/routing//34-antenna.rpt Number of pins violated: 733 Number of nets violated: 639 [INFO]: check full report here: /openLANE_flow/designs/ram_dp_bist/runs/1600x1000/reports/final_summary_report.csv [INFO]: Saving Runtime Environment [SUCCESS]: Flow Completed Without Fatal Errors.

#602 CVC step fails if MAGIC_EXT_USE_GDS=1 New issue created by stevvik I set MAGIC_EXT_USE_GDS=1 in configuration file to activate Device level LVS and got CVC step (34) failed because awk is not able to find results/magic/<design_name>.lef.spice and crashes. Here is a part of flow_summary.log: [INFO]: current step index: 34 [INFO]: Running CVC [ERROR]: during executing: "awk { /Black-box entry subcircuit/ { # remove black-box defintions while ( $1 != ".ends" ) { getline; } getline; } /^*/ { # remove comments next; } /^.ENDS .*/ { # remove name from ends lines print $1; next; } { print $0; }} /proj/memcom/memcom_tools/OpenTools/PDK/sky130/sky130A_2021.08.03_05.51.29/sky130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl /openLANE_flow/designs/ram_dp_bist/runs/full_run/results/magic/ram_dp_bist.lef.spice > /openLANE_flow/designs/ram_dp_bist/runs/full_run/results/cvc/ram_dp_bist.cdl" [ERROR]: Exit code: 1 [ERROR]: Last 10 lines: awk: cmd. line15 fatal: cannot open file `/openLANE_flow/designs/ram_dp_bist/runs/full_run/results/magic/ram_dp_bist.lef.spice' for reading (No such file or directory) [ERROR]: Please check awk log file [ERROR]: Dumping to /openLANE_flow/designs/ram_dp_bist/runs/full_run/error.log [INFO]: Calculating Runtime From the Start... [INFO]: Flow failed for ram_dp_bist/09-09_08-05 in 2h33m32s The-OpenROAD-Project/OpenLane

Does it make sense to submit OpenLane issue if I have Yosys c-code errors during ABC syntesis? The error in yosys_1.log is: ABC: + amap -m -Q 0.1 -F 20 -A 20 -C 5000 ABC: yosys-abc: src/map/amap/amapGraph.c149 Amap_ManCreateAnd: Assertion `p->nLevelMax < 4094' failed. ERROR: ABC: execution of command "/build/bin/yosys-abc -s -f /tmp/yosys-abc-HQ4iuj/abc.script 2>&1" failed: return code 134.

@User @User @User, finished that video about openlane resizing cells to meet timing:

Any advice for debugging this odd behavior?

INFO]: Obstructions added over met5 0 0 2920 3520
[INFO]: Changing layout from /Users/ronaldv/Projects/repositories/openlane/designs/sonar/runs/test/tmp/routing/46-addspacers.def to /Users/ronaldv/Projects/repositories/openlane/designs/sonar/runs/test/tmp/routing/46-addspacers.obs.def
[INFO]: Running Detailed Placement...
[INFO]: current step index: 47
OpenROAD 1 acab8e2bc2ba97db64627c8b7adfae63b55315b0
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0222] Reading LEF file: /Users/ronaldv/Projects/repositories/openlane/designs/sonar/runs/test/tmp/merged_unpadded.lef
[WARNING ODB-0220] WARNING (LEFPARS-2036): SOURCE statement is obsolete in version 5.6 and later.
The LEF parser will ignore this statement.
To avoid this warning in the future, remove this statement from the LEF file with version 5.6 or later. See file /Users/ronaldv/Projects/repositories/openlane/designs/sonar/runs/test/tmp/merged_unpadded.lef at line 862.

[INFO ODB-0223]     Created 13 technology layers
[INFO ODB-0224]     Created 25 technology vias
[INFO ODB-0225]     Created 441 library cells
[INFO ODB-0226] Finished LEF file:  /Users/ronaldv/Projects/repositories/openlane/designs/sonar/runs/test/tmp/merged_unpadded.lef
[INFO ODB-0127] Reading DEF file: /Users/ronaldv/Projects/repositories/openlane/designs/sonar/runs/test/tmp/routing/46-addspacers.obs.def
[INFO ODB-0128] Design: user_project_wrapper
[INFO ODB-0094] 		Created 100000 Insts
…
[INFO ODB-0094] 		Created 1000000 Insts
[INFO ODB-0130]     Created 645 pins.
[INFO ODB-0131]     Created 1072950 components and 4104673 component-terminals.
[INFO ODB-0132]     Created 8 special nets and 0 connections.
[INFO ODB-0133]     Created 20240 nets and 102435 connections.
[INFO ODB-0134] Finished DEF file: /Users/ronaldv/Projects/repositories/openlane/designs/sonar/runs/test/tmp/routing/46-addspacers.obs.def
[WARNING DPL-0011] Could not find power special net.
[WARNING DPL-0019] detailed placement failed on FILLER_1285_6229
[WARNING DPL-0019] detailed placement failed on FILLER_1285_6245
[WARNING DPL-0019] detailed placement failed on FILLER_1285_6257
[WARNING DPL-0019] detailed placement failed on FILLER_1285_6273
WARNING DPL-0019] message limit reached, this message will no longer print
Placement Analysis
---------------------------------
total displacement   26712575.5 u
average displacement       24.9 u
max displacement          503.0 u
original HPWL        41851298.2 u
legalized HPWL       43786853.5 u
delta HPWL                    5 %

[INFO DPL-0020] Mirrored 31538 instances
[INFO DPL-0021] HPWL before          43786853.5 u
[INFO DPL-0022] HPWL after           43755581.6 u
[INFO DPL-0023] HPWL delta               -0.1 %
[WARNING DPL-0005] Overlap check failed (54883).
 FILLER_1005_1481 overlaps FILLER_1004_1523
 FILLER_1005_1505 overlaps FILLER_1004_1511
 FILLER_1005_1513 overlaps FILLER_1005_1511
 FILLER_1005_2391 overlaps FILLER_1004_2449
 FILLER_1005_2433 overlaps FILLER_1004_2437
 FILLER_1006_2361 overlaps FILLER_1004_2397
 FILLER_1006_2394 overlaps ANTENNA__15546__B2
 FILLER_1006_3737 overlaps FILLER_1005_3732
 FILLER_1006_3749 overlaps FILLER_1006_3737
 FILLER_1006_3757 overlaps FILLER_1003_3753
 FILLER_1006_4029 overlaps ANTENNA__13213__A2_N

refuse to place most cells and fails

#596 Cannot generate pdn for my design Issue reopened by msaligane The-OpenROAD-Project/OpenLane

#604 Change and handle missing values in reports New issue created by kareefardi Currently, openlane reports

-1

for missing values, which is a legal value in some cases. However, there is a lot of dependencies on that value in the source code, so changing it needs a bit of refactoring too. The-OpenROAD-Project/OpenLane

Hi all, Any ideas what happening here?

[INFO]: Running Basic Macro Placement
[INFO]: current step index: 6
OpenROAD 1 fb8ae93b6c7a5eb0e6fac83360a8a48d76c41885
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0222] Reading LEF file: /openLANE_flow/designs/vsdbabysoc/runs/rvmyth_avsddac/tmp/merged_unpadded.lef
[WARNING ODB-0220] WARNING (LEFPARS-2036): SOURCE statement is obsolete in version 5.6 and later.
The LEF parser will ignore this statement.
To avoid this warning in the future, remove this statement from the LEF file with version 5.6 or later. See file /openLANE_flow/designs/vsdbabysoc/runs/rvmyth_avsddac/tmp/merged_unpadded.lef at line 68127.

[INFO ODB-0223]     Created 13 technology layers
[INFO ODB-0224]     Created 25 technology vias
[INFO ODB-0225]     Created 443 library cells
[INFO ODB-0226] Finished LEF file:  /openLANE_flow/designs/vsdbabysoc/runs/rvmyth_avsddac/tmp/merged_unpadded.lef
[INFO ODB-0127] Reading DEF file: /openLANE_flow/designs/vsdbabysoc/runs/rvmyth_avsddac/tmp/placement/5-replace.def
[INFO ODB-0128] Design: vsdbabysoc
[INFO ODB-0130]     Created 13 pins.
[INFO ODB-0131]     Created 1 components and 15 component-terminals.
[INFO ODB-0133]     Created 13 nets and 13 connections.
[INFO ODB-0134] Finished DEF file: /openLANE_flow/designs/vsdbabysoc/runs/rvmyth_avsddac/tmp/placement/5-replace.def
[ERROR MPL-0004] No macros found.
Error: or_basic_mp.tcl, 28 MPL-0004
[ERROR]: during executing: "openroad -exit /openLANE_flow/scripts/openroad/or_basic_mp.tcl |& tee >&@stdout /openLANE_flow/designs/vsdbabysoc/runs/rvmyth_avsddac/logs/placement/6-basic_mp.log"
[ERROR]: Exit code: 1
[ERROR]: Last 10 lines:
child process exited abnormally

If I rerun the process in interactive mode and use

run_placement

, then it would finish the placement process successfully! UPDATE: When I tried

run_floorplan

in interactive mode, the problem reproduced again but

run_placement

still works fine.

Reposting here: Can someone summarize the differences between the openlane flow and the openroad-flow-scripts ? I clearly see that there are minor difference (same basic tools used). Which flow should one use ? Any directions on the same ?

Is anyone looking into TMR capabilities in OpenLane?

Hi! Does anybody know why all opensta report files in reports/synthesis are empty? All STA results are available only in logs/synthesis dir.

Hi all, I have a

PLL

IP core in my design which generated the clock of the whole SoC. Now I’d like to know the way I can specify

PLL.CLK_OUT

pin for STA and CTS?

Dear all, I am familiarizing myself with wrapping the user project with caravel soc harness and generate a single caravel.gds file using openlane. So first i tried to use the 32bit counter example (user_proj_example) and tried these commands given below,

cd caravel_user_project/openlane/

make user_proj_example

but here is what im getting (below image), an warning that my environment is outdated and as it is warning i waited for the further openlane processing but the run just stops saying it is extracting metals ..

I have also tried updating openlane by,

cd openlane/
    git checkout master
    git pull
    make openlane
    make pdk
    make test ("make test works perfect for me")

But i have same issue while executing

make user_proj_example

. So can anyone please help me out with this?

openlane generates the powered verilog file that's then used for LVS. Is there a way to generate the verilog from the GDS? I can extract the spice netlist, but is there a way to convert that verilog?

#611 [WARNING]: The version of open_pdks installed not matching with openlane flow scripts New issue created by vijayank88 Description Whenever I make PR for latest update or install in new path I'm getting this warning message. Last time #553 .. now mismatch for open_pdks. I have installed full-pdk. Environment • Operating System Information:

uname -a

20.04.1-Ubuntu • Docker Version:

docker --version

• If you're using an alternative container service, please also include this information. • OpenLane Tag in use:

python3 ./dependencies/get_tag.py

in the main OpenLane directory. 2021.09.09_03.00.48 Reproduction Material make test will throw this warning message Expected behavior Script should match pdk version Logs

[root@48989487a315 openLANE_flow]# ./flow.tcl -design spm -tag 1stTest
[INFO]: 
	 ___   ____   ___  ____   _       ____  ____     ___
	/   \ |    \ /  _]|    \ | |     /    ||    \   /  _]
	|   | |  o  )  [_ |  _  || |    |  o  ||  _  | /  [_
	| O | |   _/    _]|  |  || |___ |     ||  |  ||    _]
	|   | |  | |   [_ |  |  ||     ||  _  ||  |  ||   [_
	\___/ |__| |_____||__|__||_____||__|__||__|__||_____|


[INFO]: Version: 2021.09.09_03.00.48-3-gecc62b4
[WARNING]: The version of open_pdks installed in the environment does not match the one required by the OpenLane flow scripts (installed: 81d28fd0423ca6bbf3f3bf00b7d407958cf8f0f3, expected: 14beb9c5386c21be5ad0d644986c839619d5f983)
child process exited abnormally
[WARNING]: OpenLane may not function properly.
[INFO]: Running non-interactively

The-OpenROAD-Project/OpenLane

#611 [WARNING]: The version of open_pdks installed not matching with openlane flow scripts Issue closed by donn The-OpenROAD-Project/OpenLane

#535 Provide support for Static IR Drop analysis in OpenLane similar to OpenROAD flow scripts Issue closed by vijayank88 The-OpenROAD-Project/OpenLane

#595 Build PDK part of the CI encountered error when doing git pull in open_pdks Issue closed by donn The-OpenROAD-Project/OpenLane

#585 Error during diode_insertion can't find opendb python module Issue closed by donn The-OpenROAD-Project/OpenLane

#537 [ERROR PDN-9999] Unexpected error: key "vccd1" not known in dictionary Issue closed by donn The-OpenROAD-Project/OpenLane

#612 Power Ring On One Layer New issue created by donn Requested by @shalan Prompt The power ring currently has vertical straps on one layer and horizontal straps on the other, using vias in the middle. These vias add considerable resistance. Proposal An option in OpenLane should be surfaced for the power ring to exist entirely on one layer. Alternatives The original setup will continue to exist. The-OpenROAD-Project/OpenLane

#617 How to change the core_area and die_area of the project. New issue created by peijunh Hello, I am running my design with OpenLane flow. I specify the core area and die area in my config.tcl as below

set ::env(DESIGN_IS_CORE) "1"

set ::env(DIE_AREA) "0 0 7000 7000"

set ::env(CORE_AREA) "50 50 6950 6950"

However, the resulting .def file in floorplan keep giving me this: DIEAREA ( 0 0 ) ( 655195 665915 ) ; When I open the design/mydesign/runs/18-09_01-38/config.tcl, I find that there are two sets of AREA. One set is at the top of this config.tcl, which is exactly what I write in my config.tcl, also shown above. The other set is around 300 lines lower, which give me this:

set ::env(CORE_AREA) "5.52 10.88 649.52 652.8

set ::env(DIE_AREA) "0.0 0.0 655.195 665.915

And I have the error in the figure, which I guess is because my area is too small. Is there anyway to specify my own die area and core area? The-OpenROAD-Project/OpenLane

#617 How to change the core_area and die_area of the project. Issue closed by donn The-OpenROAD-Project/OpenLane

Hello. I want to thank Manar for the update on common_pdn.tcl. After the update of @User  , I run my design with macro and get the error in the following figure. My macro includes a sensor and sky130_sram_4kbyte_1rw1r_32x1024_8. sensor use VDD and VSS as power pin and sram use vccd1 and vssd1 as its power pin. So I change the "set macro" in common_pdn.tcl as follows.

set macro {

orient {R0 R180 MX MY R90 R270 MXR90 MYR90}

power_pins "vccd1 VPWR VDD"

ground_pins "vssd1 VGND VSS"

blockages "li1 met1 met2 met3 met4"

straps {

}

Could anyone share suggestion and advice on this error? Thanks!

#618 routing problem for my design New issue created by peijunh Hello. I am using OpenLane to run my design. I use to way to determine the size of my design, one is to use the following config to set the size of it manually

set ::env(FP_SIZING) absolute

set ::env(DESIGN_IS_CORE) "1"

set ::env(DIE_AREA) "0 0 1000 1000"

set ::env(CORE_AREA) "50 50 950 950"

This give me this error:

4873860343726c2be203ad8b9479fa5▾

cb9e3044fcc0f058d3c5b596b19dc9e▾

I then comment the AIE_AREA, CORE_AREA and use the default setting, which set the FP_CORE_UTIL to 50. But the result give me this error: [ERROR GRT-0118] Routing congestion too high. Then I set FP_CORE_UTIL to 30 to see if I can lower the congestion. But I get the error in the following figure: So is there any suggestion on why they are happening? Thanks! The-OpenROAD-Project/OpenLane

Hey, whenever any of you submit an issue, please try to use the issue template and, by extent, upload a reproducible tarball. Like a good 80% of the time I can't do anything with just screenshots of logs.

Is there anything holding back the Low Power Standard Cell library from being supported in OpenLane? It's still not built and installed even when building the full PDK in v0.23 (unless I've done something wrong)

Hi, iam getting this error when i gave command run_floorplan. Can someone please help me solve this?