GitHub
08/10/2021, 9:38 AMVijayan Krishnan
08/10/2021, 1:14 PMGitHub
08/10/2021, 1:45 PMKashif Inayat
08/11/2021, 5:26 PMEugene Stolbikov
08/12/2021, 8:22 AMGitHub
08/12/2021, 10:09 AMEugene Stolbikov
08/13/2021, 8:23 AMDELAY/AREA 0-3/0-2
?
Are my guesses correct, that:
S1=DELAY 0,
S2=DELAY 1,
S3=DELAY 2,
S4=DELAY 3,
S5=AREA 0,
S6=AREA 1,
S7=AREA 2.
If yes, it would be better to write this in explicit form in generated HTML.
Also, the exploration results are quite strange.
UPD: I have checked tcl scripts and confirmed, that my guesses are correct! But it still better to write this in explicit form somewere.Eugene Stolbikov
08/13/2021, 9:16 AMGitHub
08/13/2021, 10:14 AMIndira Iyer
08/14/2021, 7:43 AMGitHub
08/14/2021, 10:49 AMGitHub
08/14/2021, 9:08 PMGitHub
08/14/2021, 10:15 PMGitHub
08/15/2021, 9:07 AMGitHub
08/15/2021, 9:07 AMGitHub
08/15/2021, 9:09 AMGitHub
08/15/2021, 9:14 AMGitHub
08/15/2021, 12:08 PMGitHub
08/16/2021, 2:46 PMGitHub
08/16/2021, 2:59 PMGitHub
08/16/2021, 7:14 PMMitch Bailey
08/17/2021, 3:16 AM(no matching pin) |cpu_mask_n[0]
(no matching pin) |ram_ce_e
cpu_mask_n[0] |(no matching pin)
ram_ce_e |(no matching pin)
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Cell pin lists for hs32_core1 and hs32_core1 altered to match.
Cells failed matching, or top level cell failed pin matching.
This from the caravel-Hs32core
of mpw-1. In the schematic here, you can also see that the gate level verilog contains a buffer with a floating output. It looks like the layout is what is intended.
What program outputs the final placement gate level verilog and who is the contact person? Or has this already been fixed?GitHub
08/17/2021, 6:10 AMGitHub
08/17/2021, 6:51 AMGitHub
08/17/2021, 9:50 AMGitHub
08/17/2021, 11:03 AMGitHub
08/17/2021, 11:37 AMGitHub
08/18/2021, 1:42 AMGitHub
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08/18/2021, 11:58 AM