@User OR has added basic NDR support recently. If you test it out we would be glad to get any feedback. Its still pretty new code so you might hit some bumps

Hi, I have one question, I have my design finish without fatal errors in openlane, but I have a lot of antenna violations in the user project, 0 in the wrapper. How I can debug/fix these issues? any configuration that I can use in openlane to fix that?. Also I don't know how critical this issues are.

Also I found this message in openlane during my inspection of the user project example.

Warning: Some pins weren't matched by the config file
Those are: ['user_clk', 'irq[0]', 'irq[1]', 'irq[2]']
Assigning random sides to the above pins

I thought that the pins position is something that we can not change. This pins need to be defined by us?

My flow now gets an error during final GDS:

[ERROR]: during executing: "python3 /openLANE_flow/scripts/magic_drc_to_tr_drc.py -i /project/openlane/user_project_wrapper/runs/user_project_wrapper/reports/magic/41-magic.drc -o /project/
openlane/user_project_wrapper/runs/user_project_wrapper/reports/magic/41-magic.tr.drc"                                                                                                       
[ERROR]: Exit code: 1                                                                                                                                                                        
[ERROR]: Last 10 lines:                                                                                                                                                                      
child killed: kill signal                                                                                                                                                                    
                                                                                                                                                                                             
[ERROR]: Please check python3  log file                                                                                                                                                      
[ERROR]: Dumping to /project/openlane/user_project_wrapper/runs/user_project_wrapper/error.log

The error.log just has the kill signal too. Any idea? This seems similar to the error I get when I last ran the precheck...

I got those when it ran out of memory.

Had to add more to my machine (16GB).

@User ^^

Total online memory: 64G

Hi all, I’ve been trying to understand a bit more about how LVS using Netgen works, and it looks to me like the OpenLANE flow performs this check by comparing a Verilog netlist outputted by OpenROAD with a Spice netlist extracted from the final design layout. I’m curious though why the flow doesn’t use the Verilog netlist output by Yosys after synthesis — wouldn’t that be closer to the intent of LVS, to ensure that OpenROAD doesn’t make any transformations that break from the original design?

Is it possible to remove the dangling power/ground net in Openlane? For example, the power/ground nets on M4 in between two macros are placed close together vertically; however, these nets are not connected to the power/ground nets on M5 because they are too short. These nets cause LVS errors because these nets are extracted as vssa1_uq0 which does not exist in the netlist.

Hi, I want to use basic PDK Sky130 cells for part of my design. I manage to make it work with RTL simulations. But when I try to use the same code to be process by openlane I get and error in that part because it does not recognize the cells. How I need to configure openlane to allow to use basic cells ? thanks

I am unable to get OpenLane to compile my project. It errors in fast route without any reason See attached files for details.

Issue reproducible with caravel mpw-one-final too. It might be due to Magic being latest version?

image.png

Hello, I was trying to run OpenLane in interactive mode. I wanted to know the significance of the command "run_powered_verilog". What does it do?

I also would like to ask that, if I have DRC errors in my design and I corrected them in the .mag file using magic. How can I re-insert the corrected design into the OpenLane flow?

I'm interviewing @User about OpenROAD. What questions do you have?

Hello, I was trying to connect my module with the top module user_analog_project_wrapper(caravan). I am not sure how to use the lef file of user_analog_project_wrapper since it seems like I cannot use set ::env(EXTRA_LEFS) for the top module. The pin location will be random if I don't use that lef file.

Hi, everyone. I am trying to connect my module with the top module user_analog_project_wrapper(caravan). The supply voltage of my module is 3.3V and I would like to use lv2hv level converter in hvl library to convert the input signal from 1.8v to 3.3v. I tried to insert lv2hv into my top-level verilog file but I got an error. The level converter verilog includes the cell udp_pwr_good_pp and that cell is defined as "primitive" which causes error in yosys. Does anyone know how to solve this issue or if there is other method to use this lv2hv cell? Thank you.

I have a design with a number of asynchronous paths (that I made on purpose) that successfully synthesized via openlane and I was hoping to run a back-annotated simulation on them. I didn’t see a way to do that and as it’s not the largest design (maybe ~2K cell) so I thought I might try to spice it via the extracted lvs netlist. And, although functional, it’s way too slow. So I noticed the PDK has support for irsim in the file below, which would be perfect. sky130A/libs.tech/irsim/sky130A_1v80_27.prm But I couldn’t find the ::env var to set to generate the needed .sim file. I found the TCL script that runs magic, and asked it to generate the file like this: openlane/scripts/tcl_commands/magic.tcl @@ -175,9 +175,13 @@ if { ! $::env(LVS_CONNECT_BY_LABEL) } { # extract warn all extract + ext2spice lvs ext2spice -o $::env(EXT_NETLIST) $::env(DESIGN_NAME).ext feedback save $::env(magic_log_file_tag)_ext2$extract_type.feedback.txt + +ext2sim run + And it did generate the .sim file, but it only had one line: results/magic/my_design.sim | units: 500000 tech: sky130A format: MIT I am guessing I am probably missing something obvious. Has anyone gotten this to work?

Hello! I am getting this error for fastroute in openlane, what is possibly the issue? Is it because the routing is too complex to finish?

I am having issues with openlane. Following the guide and doing following: make openlane make full-pdk

make test It gives following error: "exec grep "#Antenna violations:" [index_file $::env(fastroute_log_file_tag).log 0] -s | tail -1 | sed -r "s/.*\[^0-9\]//"" (procedure "global_routing_fastroute" line 16) invoked from within "global_routing_fastroute" (procedure "global_routing" line 10) invoked from within "global_routing" (procedure "run_routing" line 27) invoked from within "run_routing" (procedure "run_non_interactive_mode" line 19) invoked from within "run_non_interactive_mode {*}$argv" invoked from within "if { [info exists flags_map(-interactive)] || [info exists flags_map(-it)] } { puts_info "Running interactively" if { [info exists arg_values(-file)..." (file "./flow.tcl" line 223)

The issue seems that # Antenna violations is not found in log

I checked for rc7, v0.12, v0.15, v0.21 (Git clone according branch AND same docker image)

Same issue

Can somebody help me fix it?

[The-OpenROAD-Project/OpenLane] Issue opened by loverdec

[The-OpenROAD-Project/OpenLane] Issue opened by getziadz

Hello, I am using openlane to put my macro into the user wrapper. But I am meeting this error, as shown in the first figure. My macro also contains some macro, those macros' layout are in the gds and lef file, but they are still macro in the verilog of my macro. Thus I also have the warning in the second figure. dccm_0___sky130_sram__4kb and u_tempsense1 are both my macro. among them dccm_0___sky130_sram__4kb are sram thus only have behaviour verilog. I suspect the first error is because of the warning in the second figure. Is there any suggestion on fixing the warning? Or probably the error is not due to the warning?