#298 OpenSTA unable to finish Issue opened by cgreen18 Describe the bug Running flow on the provided test design, spm, works as intended. When running the flow on a much larger design, the flow fails to finish synthesis. The flow successfully finished Yosys but fails during the scripts/sta.tcl portion of the flow. Specifically, the flow successfully reads scripts/base.sdc but fails on report_tns (line 28 of sta.tcl). It also fails/never completes when calling report_wns (line 30 of sta.tcl). The debug information is uninformative. To Reproduce The error is encountered for my team's ASIC verilog file. The flow is run on a the source code file: top_level_bASIC.generic.v The verilog module is named "top_level_bASIC" and so is the design name. Unknown how to reproduce for other designs/source code. Expected behavior Expected to finish flow. It freezes until "Child killed" see below. Screenshots Command: ./flow.tcl -design top_level_bASIC The exact terminal output from the above command is given below. Note, the first portion is some output from reading base.sdc. set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs] set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0] puts "[INFO]: Setting load to: $cap_load" [INFO]: Setting load to: 0.01765 set_load $cap_load [all_outputs] [ERROR]: during executing: "sta /openLANE_flow/scripts/sta.tcl |& tee >&@stdout /openLANE_flow/designs/top_level_bASIC/runs/22-04_00-17/logs/synthesis/2-opensta" [ERROR]: Exit code: 1 [ERROR]: Last 10 lines: child killed: kill signal [ERROR]: Please check sta log file [ERROR]: Dumping to /openLANE_flow/designs/top_level_bASIC/runs/22-04_00-17/error.log [INFO]: Calculating Runtime From the Start... [INFO]: Flow failed for top_level_bASIC/22-04_00-17 in 0h53m39s [INFO]: Generating Final Summary Report... [INFO]: Design Name: top_level_bASIC Run Directory: /openLANE_flow/designs/top_level_bASIC/runs/22-04_00-17 Source not found. LVS Summary: Source: /openLANE_flow/designs/top_level_bASIC/runs/22-04_00-17/results/lvs/top_level_bASIC.lvs_parsed.gds.log Source not found. Antenna Summary: No antenna report found. [INFO]: check full report here: /openLANE_flow/designs/top_level_bASIC/runs/22-04_00-17/reports/final_summary_report.csv [ERROR]: Flow Failed. while executing "try_catch sta $::env(SCRIPTS_DIR)/sta.tcl |& tee $::env(TERMINAL_OUTPUT) [index_file $::env(opensta_log_file_tag) 0]" (procedure "run_sta" line 8) invoked from within "run_sta" (procedure "run_synthesis" line 12) invoked from within "run_synthesis" (procedure "run_non_interactive_mode" line 14) invoked from within "run_non_interactive_mode {*}$argv" invoked from within "if { [info exists flags_map(-interactive)] || [info exists flags_map(-it)] } { puts_info "Running interactively" if { [info exists arg_values(-file)..." (file "./flow.tcl" line 223) Desktop (please complete the following information): • OS: CentOS-7 running w/ 4GB RAM and sufficient disk sapce • Openlane Versions rc4, rc7, and v0.12. hash: bee14bb • open_pdks Version hash: b9ffc1fd1cfc26cbca85a61c287ac799721f6e6a • skywater-pdk Version hash: db2e06709dc3d876aa6b74a5f3893fa5f1bc2a6e Additional context The source code is a generic netlist generated by a separate process. efabless/openlane

⚠️ Action required - upgrade app for skywater-pdk ⚠️

#299 Request for documentation or pointer to documentation Issue opened by bhawandeepsingh Is your feature request related to a problem? Please describe. A clear and concise description of what the problem is. Ex. I'm always frustrated when [...] I need to floorplan and place multiple projects - riscv, memories, uart etc rather than combining them into a single heirarchical project. My first approach was to synthesize them as separate projects and proceed. Now I remember openlane expects projects to follow a given directory structure and possibly all relevant files to be present in a common location for a particular stage. Hence, not sure how to go ahead with it. Describe the solution you'd like A clear and concise description of what you want to happen. Can you provide a link to instructions for doing this ? Thanks Describe alternatives you've considered A clear and concise description of any alternative solutions or features you've considered. Additional context Add any other context or screenshots about the feature request here. efabless/openlane

Hello all, I have a basic question regarding open_lane design setup. How can tell ./flow.tcl to take a design from a folder not under open_lane instalallation.

Although if I mention

./flow.tcl -design <design_path>

openlane is trying to look under

/openLANE_flow/designs/

Hello again, how can I solve this error

[ERROR PPL-0024] Number of pins (815) exceed max possible (692)

Error: or_ioplacer.tcl, 50 PPL-0024

. By setting

FP_CORE_UTIL

to 10 I could get around this, but then it results in

Begin NesterovInit

End NesterovInit

[NesterovSolve] Iter: 1 overflow: 0.793887 HPWL: 533933486

[ERROR GPL-0306] RePlAce divergence detected.

Please decrease init_density_penalty value

Error: or_replace.tcl, 94 GPL-0306

. Yet to debug this though

Hi, so I've generated a netlist for a design through Genus and I am trying to use that netlist in openlane to do pnr. The initial steps till the detailed placement steps are successful, however the flow fails at cts stage with the following error:

Error: or_cts.tcl, 29 cannot read file /home/merl-tools/openlane-v0.9/openlane/designs/Ibtida_test_genus_netlist/runs/Ibtida_top_dffram_cv.synthesis.v.

The reason for using a netlist generated through genus was to understand and do a comparison for the purpose of PPA benchmarking, but it won't go through cts stage. Has anyone else tried this before?

Do we need the mpw-one-b tag to work or is that one obsolete? Asking because it currently fails

make pdk

because of the skywater-pdk main branch renaming so migh t want to add a makefile fix and move that tag

Hello everyone,

I was checking on antenna, using magic and using openroad antenna checker, the first one gives me a violation and the second one gives me a clean report. So, If this happens with someone before, What I have to do in this case?

Hello everyone, There is something I wanted to ask about if it happens with someone before. on checking on the drcs on magic inside openroad on typing

run_magic_drc

i found that there is no violations but when I open magic gui I found a huge number of drc violations. so if this happens with someone before, what I have to do in this case?

what's the xor stuff that's happening in rc0.12? can I turn it off, or is it needed for the pre check script?

⚠️ Action required - upgrade app for skywater-pdk ⚠️

#303 ROUTING_OPT_ITERS no longer works Issue opened by mattvenn Describe the bug set ::env(ROUTING_OPT_ITERS) 100 should set the number of routing iterations to 100. Instead it is stuck at 64. To Reproduce On a congested design that takes longer than 64 iterations to route, increase iterations to a larger number: set ::env(ROUTING_OPT_ITERS) 100 Expected behavior router should keep going past 64th iteration Screenshots Desktop (please complete the following information): • OS: Ubuntu 20.04 • Openlane Version 0.12 • open_pdks Version:f788cea • skywater-pdk Version: db2e067 efabless/openlane

Hi everyone. I wrote a bit about the work that @User and I are working on around OpenLANE to make it easier to onboard existing designs https://olofkindgren.blogspot.com/2021/04/a-first-look-at-edalize-for-asic-flows.html

I would like to do some [CI on the subservient SoC using OpenLANE](https://github.com/olofk/subservient/issues/1). Saw that the CI for OpenLANE itself was recently overhauled. Is it @User I should talk to about this, or do other people know how this works?

So, I'm having some issues wrapping my head around this docker stuff. IIUC the

make openlane

step takes a centos image, extracts and adds the contents of the tar balls in the repo and creates a new image called e.g. openlane:rc6

But this final image only exist locallly, right? What do I need to do if I want to run my design through the openlane flow in a CI system? Does the CI system download the image from somewhere, or does it repeat the steps I do normally?

And what about the pdks? It's 4GB of stuff in there. Do I need all that? And do I need to run

make pdk

every time or can I store something prebuilt somewhere?

Ok, so there's 1.5GB of conda packages inside the PDK?!?!

Another thing that confuses me a bit is that it seems like I'm building one docker image (openlane:rc6) but then launches a completely different one (efabless/<openlane:v0.12>) How does it all fit together?

Check the thread ->

Thanks

Is there documentation of the PDN creation anywhere? I'm looking at examples in the Caravel design that create their own pdn.tcl script. Is there an overview of the requirements for this?

Can anyone tell me if openlane builds are reproducable at this point? I'm getting slighly different resutls on rebuilds but not sure if that is on my side or if parts of the toolchain don't guarantee reproducability

Doing a rebuild of a super simple project it seems to be equivalent up to the resizer step

Sweet! I now have Github actions building my subservient SoC through OpenLane with FuseSoC on every push. And it's easy for everyone to add to their own projects as well. Check it out! https://github.com/olofk/subservient/actions

Happy to help out if you want to enable the same for your own projects

And now we have the same thing for the OpenLANE examples. @User already wrote FuseSoC core description files for most of them, so I just added CI steps to run them. Started with just spm and inverter to get shorter runtime during the experiments, but it's just a matter of adding a line each for the other projects https://github.com/olofk/openlane-examples/actions

Can anyone help with this ? I wrote ./flow.tcl -interactive in the command line after fresh installation of the openlane. I am getting this unexpected error.