can anyone give me a hand with reading the antenna report?

so I see this as a report for the clk line connecting to a dff. showing all the layers the signal passes through, and calculating area

I remember from a previous discussion (can't find it now) that ratio needs to be < 400 to pass

but I also have this one:

and my design reports no antenna violations

so not sure if I'm reading the report correctly

thanks!

#172 Fix permissions on TCL files Pull request opened by antonblanchard efabless/openlane Travis CI: Build Created

#172 Fix permissions on TCL files Pull request merged by agorararmard efabless/openlane

#173 yosys synthesis thinks macro is combinatorial Issue opened by antonblanchard Looking through the log files, I notice

yosys

complains that my macro is combinatorial (it isn't):

ABC: + retime -D -D 15000 -M 6 
ABC: + scleanup 
ABC: Error: The network is combinational.

We call retime again later on (with a different strategy), and this time it works:

ABC: + fraig_store 
ABC: + fraig_restore 
ABC: + map 
ABC: + 
ABC: + retime -D -D 15000

Are we missing a step before the first retime that inserts sequential elements? efabless/openlane

#174 Quick Start instructions fail on

make pdk

with "the input device is not a TTY" Issue opened by tommythorn Looks like a Docker related issue. $ docker --version Docker version 19.03.13, build 4484c46 Full build: build.log ](url) efabless/openlane

I've just installed rc6 from scratch and a design that was working on rc6 I installed on another computer is now failing with [CRIT] [PDNG-0030] Layer specified for std. cell rails '$::env(FP_PDN_RAILS_LAYER)' not in list of layers.

anyone seen this?

same for spm

but make test works...

doh I got it, had updated my .bashrc alias for starting openlane but not sourced it yet...

#175 About constraints Issue opened by sultanbepari Sir in .sdc file what constraints can we modify except that time....can we modify area, power, clock frequency etc. Plz respond efabless/openlane

#176 Diode strategy 2 (and 5) fails in spice extraction (illegal overlaps) Issue opened by antonblanchard The following test case icache.tar.gz fails with:

Extracting icache into icache.ext:
icache: 210688 fatal errors
Total of 210688 errors (check feedback entries).
exttospice finished.
Using technology "sky130A", version 1.0.110-0-gd6807dc
[ERROR]: There are illegal overlaps (e.g., routes over obstructions) in your design.
[ERROR]: See /openLANE_flow/designs/icache/runs/24-01_03-47/logs/magic/43-magic_ext2spice.feedback.txt for more.

efabless/openlane

#177 cugr doesn't support inout ports Issue opened by antonblanchard This was noticed in issue #167

[   0.006] ------------------------------------------------------------------------------ 
[   0.015]                      ICCAD 2019 - Global Routing Contest                       
[   0.015]                              Team number : 15                                  
[   0.015]                              Team name : CU-GR                                 
[   0.015]         Members: Jinwei Liu, Chak-Wa Pui, Fangzhou Wang,                       
[   0.015]                  Evangeline F.Y. Young                                         
[   0.015]         Affiliation: The Chinese University of Hong Kong                       
[   0.015] ------------------------------------------------------------------------------ 
[   0.021] Input .lef file   : /openLANE_flow/designs/icache/runs/24-01_19-07/tmp/merged_unpadded.lef
[   0.021] Input .def file.  : /openLANE_flow/designs/icache/runs/24-01_19-07/tmp/routing/23-addspacers.obs.def
[   0.021] # of threads      : 32
[   0.021] Output file name  : /openLANE_flow/designs/icache/runs/24-01_19-07/tmp/routing/24-fastroute.guide
[   0.021] 
terminate called after throwing an instance of 'Rsyn::Exception'
  what():  Only in and out direction are supported right now.

efabless/openlane

#167 TritonRoute failure results in report_generation_wrapper.py endless loop Issue closed by antonblanchard efabless/openlane

#174 Quick Start instructions fail on

make pdk

with "the input device is not a TTY" Issue closed by tommythorn efabless/openlane

@User @User have you had any luck updating openroad in openlane very recently? I've been struggling with a couple of DRC violations that I tried to reproduce directly in openroad, but it ran clean. So I went down the rabbit hole of updating the docker image and ended up here: https://github.com/The-OpenROAD-Project/OpenROAD/issues/567

I want to compile a list of videos about Openlane, Caravel and Sky130 as introductory material : https://docs.google.com/spreadsheets/d/1fM301JZe_2h0-mTfyahFGRWqt3fDhnnSe2X3_pM5GKI/edit#gid=0 Please add any videos you think are important and missing.

in openlane rc6 branch ,i am getting error cannot open /.sta,is that mean opensta is not present in docker

#178 Make sure the OpenROAD / OpenLane and SKY130 flow works well with edalize Issue opened by mithro edalize is probably the most popular library for interfacing to EDA tooling and used by the FuseSoC tooling which is used by both OpenTitan and SWERV line from Western Digital. It would be good to make sure that Edalize / FuseSoC supports OpenLane / OpenROAD tooling and able to produce manufacturable GDS from a FuseSoC design. Related issue olofk/edalize#215 efabless/openlane

#176 Diode strategy 2 (and 5) fails in spice extraction (illegal overlaps) Issue closed by antonblanchard efabless/openlane

Please write how to do workaround for an issue https://github.com/google/skywater-pdk/issues/295

I can't install openlane on my PC

#179 TritonRoute creates new via2_FR/via4_FR vias Issue opened by antonblanchard This doesn't appear to cause problems, but it's a bit strange that TritonRoute creates new via2_FR/via4_FR vias. Ahmed confirms that we should be providing it in the techLEF:

Warning: met2 does not have viaDef align with layer direction, generating new viaDef via2_FR...
Warning: met4 does not have viaDef align with layer direction, generating new viaDef via4_FR...

efabless/openlane

I get a bunch of these when hardening my DFFRAM based macro:

[WARNING GRT-0009] missing route to pin LBANK.COLUMN\[1\].RAMCOLS.B_0_0.SLICE\[7\].RAM8x32.WORD\[5\].<http://W.B3.CG/CLK|W.B3.CG/CLK>

Not sure if missing routes are sometimes expected, or a bug