tnt
11/29/2020, 6:16 PMmprj.clk
looks like a clock net spec for the wrapper, not for the inside code.Jean
11/29/2020, 6:17 PMtnt
11/29/2020, 6:18 PMCLOCK_PORT
and not have CLOCK_NET
at all ...Jean
11/29/2020, 6:19 PMtnt
11/29/2020, 6:20 PMJean
11/29/2020, 6:20 PMtnt
11/29/2020, 6:20 PMJean
11/29/2020, 6:21 PMGitHub (Legacy)
11/29/2020, 7:40 PMPhilipp Gühring
11/29/2020, 7:41 PMJean
11/29/2020, 8:09 PMtnt
11/29/2020, 8:12 PMtnt
11/29/2020, 8:12 PMJean
11/29/2020, 8:13 PMtnt
11/29/2020, 8:13 PMtnt
11/29/2020, 8:13 PMJoel Sanchez
11/29/2020, 8:17 PMtnt
11/29/2020, 8:23 PMtnt
11/29/2020, 8:23 PMJoel Sanchez
11/29/2020, 8:23 PMtnt
11/29/2020, 8:24 PMJecel Assumpção Jr
11/29/2020, 8:35 PMJecel Assumpção Jr
11/29/2020, 8:42 PMHanssel Enrique Morales Norato
11/29/2020, 8:47 PMJecel Assumpção Jr
11/29/2020, 8:54 PMJean
11/29/2020, 8:56 PMmake user_proj_example
Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/results/placement/user_proj_example.placement.def
[INFO]: Setting output delay to: 2.0
[INFO]: Setting input delay to: 2.0
[INFO]: Setting load to: 0.01765
[INFO]: Configuring cts characterization...
[INFO]: Performing clock tree synthesis...
[INFO]: Looking for the following net(s): mprj.clk
Error: Error when finding -clk_nets in DB!
Huh?tnt
11/29/2020, 8:58 PMJean
11/29/2020, 9:52 PMmake user_proj_example
with default openlane/user_proj_example.v does not seem to need a pdn.tcl file
With my verilog in openlane/user_proj_example.v it requires one.
Not sure why?
So if I copy openlane/user_project_wrapper/pdn.tcl I get
[CRIT] [PDNG-9999] Unexpected error: Error: pdn.tcl, 18 can't read "::env(_WIDTH)": no such variable
same for env vars _VDD_NET_NAME and _GND_NET_NAME. How should I define them in config?tnt
11/29/2020, 10:11 PMJean
11/29/2020, 10:11 PM