Tim Edwards
11/28/2020, 1:50 AMopenlane/custom_cells/verilog
, but there is no such directory in the open_pdks sources. Do you need to send a pull request?aryap
11/28/2020, 2:53 AMchild killed: segmentation violation
during or_route.tcl
- is this a design problem or a bug?drr
11/28/2020, 8:29 AMWajeh ul hasan
11/28/2020, 8:46 AMspm
, however its not getting connected with the grid. Any ideas? @User @User @UserJoel Sanchez
11/28/2020, 10:49 AMDEF file write success !! location : /project/openlane/DFFRAM/runs/DFFRAM/results/placement/DFFRAM.placement.def
-------------------------------------------------------------------
tasks Wtime Ctime
Parser 0.630 0.310
resgin assign 0.632 0.310
pre-placement 0.632 0.310
non Group cell placement 0.674 0.330
All 0.681 0.330
- - - - - EVALUATION - - - - -
AVG_displacement : 2936.64
SUM_displacement : 7.49049e+07
MAX_displacement : 49550
- - - - - - - - - - - - - - - -
[ERROR]: during executing: "opendp -lef /project/openlane/DFFRAM/runs/DFFRAM/tmp/merged.lef -def /project/openlane/DFFRAM/runs/DFFRAM/tmp/placement/replace.def -output_def /project/openlane/DFFRAM/runs/DFFRAM/results/placement/DFFRAM.placement.def |& tee >&@stdout /project/openlane/DFFRAM/runs/DFFRAM/logs/placement/opendp.log"
[ERROR]: Exit code: 1
[ERROR]: Last 10 lines:
child killed: segmentation violation
[ERROR]: Please check opendp log file
[ERROR]: Dumping to /project/openlane/DFFRAM/runs/DFFRAM/error.log
while executing
"try_catch opendp -lef $::env(MERGED_LEF) -def $::env(CURRENT_DEF) -output_def $::env(opendp_result_file_tag).def |& tee $::env(TERMINAL_OUTPUT) $:..."
(procedure "detailed_placement" line 4)
invoked from within
"detailed_placement"
(procedure "run_placement" line 16)
invoked from within
"run_placement"
(procedure "run_non_interactive_mode" line 13)
invoked from within
"run_non_interactive_mode {*}$argv"
invoked from within
"if { [info exists flags_map(-interactive)] || [info exists flags_map(-it)] } {
puts_info "Running interactively"
if { [info exists arg_values(-file)..."
(file "/openLANE_flow/flow.tcl" line 164)
Makefile:24: fallo en las instrucciones para el objetivo 'DFFRAM'
make: *** [DFFRAM] Error 1
I am not sure if I may be missing something, so apologies in advance 🙂Matt Aamold
11/28/2020, 2:38 PMuser_proj_example/config.tcl
and modifying it appropriately. I then commented out set ::env(DIE_AREA)
setting of 0 0 600 600
since that is fairly small (and the design needs more room). When I do this, the core area remains very small and modifying set ::env(PL_TARGET_DENSITY
has no effect. Of course this then results in a RePlAce error saying Filler area is negative!! Please put higher target density or Re-floorplan to have enough coreArea
. If I uncomment set ::env(DIE_AREA)
and adjust manually, I get past the core area issues. So my questions are, 1.) where is the default core area parameter being set when DIE_AREA
setting is commented out in the config.tcl? 2.) For this option (option 1) of hardening our design, is setting DIE_AREA
to specific values required?Joel Sanchez
11/28/2020, 5:25 PM5. Executing Verilog-2005 frontend: /project/openlane/user_project_wrapper/../../verilog/rtl/custom_core/inc/core_types.vh
/project/openlane/user_project_wrapper/../../verilog/rtl/custom_core/inc/core_types.vh:9: ERROR: syntax error, unexpected TOK_ID, expecting ',' or '=' or ';' or '['
[ERROR]: during executing: "yosys -c /openLANE_flow/scripts/synth.tcl -l /project/openlane/user_project_wrapper/runs/user_project_wrapper/logs/synthesis/yosys.log |& tee >&@stdout"
[ERROR]: Exit code: 1
[ERROR]: Last 10 lines:
child process exited abnormally
[ERROR]: Please check yosys log file
[ERROR]: Dumping to /project/openlane/user_project_wrapper/runs/user_project_wrapper/error.log
As you can see, it reports a syntax error on _core_types.vh_ file but looking at the file it is a simple function:
function automatic is_r_type_instr;
input logic [`INSTR_OPCODE_RANGE] opcode;
begin
is_r_type_instr = 1'b0;
if ( (opcode == `INSTR_ADD_OPCODE)
|(opcode == `INSTR_SUB_OPCODE)
|(opcode == `INSTR_SLL_OPCODE)
|(opcode == `INSTR_SRL_OPCODE)
|(opcode == `INSTR_ADDI_OPCODE))
is_r_type_instr = 1'b1;
end
endfunction
It is important to note that the feature I am trying to integrate within caravel is functional and has been tested on a different environment. It compiles fine with verilator and I am able to perform simulations, so I am not sure if the issue is on yosys side. Looking at the slack messages I saw that someone had a similar problem and it was related to yosys and some problems supporting System Verilog. I would appreciate if someone can confirm that yosys do not support SV or if I need to add some special define/parameter on the Makefiles to be able to use System Verilog on my design. It is important to note that my design is pretty big and it is entirely done with SV so it is unlikely that I can change all code to verilog in a couple days.tnt
11/28/2020, 5:27 PM-sv
flag to the read_verilog
command for it to work at all.tnt
11/28/2020, 6:03 PMdevelop
? Or am I missing something ? Because AFAICT it generates a giant grid met4
/ met5
and just completely goes over everything including the macro, shorting everything.Anish
11/28/2020, 9:55 PMAnish
11/28/2020, 9:56 PMaryap
11/28/2020, 10:48 PMUpdate congestion history type 2
[INFO] iteration 35, enlarge 181, costheight 244, threshold 0 via cost 0
[INFO] log_coef 0.507043, healingTrigger 15 cost_step 2 L 1 cost_type 1 updatetype 2
end grid wrong y2 x2 [1 114] , net start [75 175] routelen 139
checking failed 19191
(or_route.tcl then aborts)tnt
11/28/2020, 10:54 PMJoel Sanchez
11/28/2020, 11:21 PM21.3 Executing FLATTEN pass (flatten design).
[ERROR] during executing "yosys -c /openLANE_flow/scripts/synth.tcl -l /project/openlane/user_project_wrapper/runs/user_project_wrapper/logs/synthesis/yosys.log |&...
I tried increasing the _DIE_AREA_ to "0 0 2920 3520" but still see the same error so I was wondering if you could point me in the right direction in order to know how should I determine the rest of variables to be able to make progress. Looking at the README file I cannot see what approach should I follow. Thanks.Anish
11/28/2020, 11:22 PMAnish
11/28/2020, 11:22 PMtnt
11/28/2020, 11:28 PMdrr
11/29/2020, 3:23 AMMatt Aamold
11/29/2020, 5:08 AMCLOCK_PERIOD
, CLOCK_PORT
, and CLOCK_NET
from the config.tcl
are honored and the SDC_FILE
does nothing. I tried to create multiple clocks in the SDC_FILE
, but only the single clock referenced in the config.tcl
were analyzed. Can you specify multiple clocks in the config.tcl
file?Aireen Amir Jalal
11/29/2020, 5:45 AMAnish
11/29/2020, 6:49 AMWajeh ul hasan
11/29/2020, 11:57 AMJean
11/29/2020, 5:33 PMNotice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/placement/replace.def
Warning: could not find power special net
Design Stats
--------------------------------
total instances 398959
multi row instances 0
fixed instances 135872
nets 263165
design area 10173980.2 u^2
fixed area 176439.2 u^2
movable area 3873665.2 u^2
utilization 39 %
utilization padded 65 %
rows 1286
row height 2.7 u
Warning: detailed placement failed on _417365_
Warning: detailed placement failed on _219169_
Warning: detailed placement failed on _219098_
Warning: detailed placement failed on _218128_
Warning: detailed placement failed on _417025_
Warning: detailed placement failed on _219362_
Thousands of these detailed placement warning
Project and runs checked in at https://github.com/miscellaneousbits/caravel_sha3_256_crypto_miner.git branch miner project user_proj_example.
Any ideas why?tnt
11/29/2020, 5:36 PMtnt
11/29/2020, 5:36 PMJean
11/29/2020, 5:51 PMWarning: could not find power special net
have any significance?tnt
11/29/2020, 5:51 PMJean
11/29/2020, 6:14 PMtnt
11/29/2020, 6:15 PMJean
11/29/2020, 6:16 PM