GitHub (Legacy)
11/23/2020, 8:18 PMNadeem Yaseen
11/24/2020, 7:13 AMWajeh ul hasan
11/24/2020, 7:47 AMsky130_fd_sc_hd includes clock-gating cells to reduce active power during non-sleep modes
what is the name of the cell? skywater_fd_sc_hd__xx
?Philipp Gühring
11/24/2020, 7:50 AMPhilipp Gühring
11/24/2020, 7:50 AMWajeh ul hasan
11/24/2020, 6:39 PM[ERROR] FastRoute cannot handle very congested design
[ERROR]: during executing: "openroad -exit /openLANE_flow/scripts/openroad/or_route.tcl |& tee >&@stdout /openLANE_flow/designs/ghazi/runs/fourth/logs/routing/fastroute.log"
[ERROR]: Exit code: 1
[ERROR]: Last 10 lines:
child process exited abnormally
From the DEF file, the standard cells are being overlapped with the macro. Usually there is a placement blockage placed over the macro to avoid this.
I could not find how to do it in OPENLANE flow.
Reviewing the OPENROAD git, they have a way to create a fence around the macro, as shown below:
https://github.com/The-OpenROAD-Project/OpenROAD/blob/master/src/TritonMacroPlace/src/macroPlace.tcl
@User @Useraryap
11/25/2020, 12:39 AMAnish
11/25/2020, 1:36 AMPL_BASIC_PLACEMENT
strictly required on rc5?Anish
11/25/2020, 1:36 AMAnish
11/25/2020, 1:38 AMHanssel Enrique Morales Norato
11/25/2020, 2:10 AMJean
11/25/2020, 3:23 AMLayer 1 overflow: 0
Layer 2 overflow: 0
Layer 3 overflow: 0
Layer 4 overflow: 0
Layer 5 overflow: 0
Layer 6 overflow: 0
[Overflow Report] Total Usage : 4308733
[Overflow Report] Total Capacity: 13724068
[Overflow Report] Max H Overflow: 0
[Overflow Report] Max V Overflow: 0
[Overflow Report] Max Overflow : 0
[Overflow Report] H Overflow : 0
[Overflow Report] V Overflow : 0
[Overflow Report] Final Overflow: 0
[INFO] Final usage : 4308733
[INFO] Final number of vias : 1244036
[INFO] Final usage 3D : 8040841
[INFO] Total wirelength: -219538 um
[ERROR]: during executing: "openroad -exit /openLANE_flow/openlane/scripts/openroad/or_route.tcl |& tee >&@stdout /openLANE_flow/openlane/designs/sha3_miner/runs/25-11_03-03/logs/routing/fastroute.log"
[ERROR]: Exit code: 1
[ERROR]: Last 10 lines:
child killed: segmentation violation
[ERROR]: Please check openroad log file
[ERROR]: Dumping to /openLANE_flow/openlane/designs/sha3_miner/runs/25-11_03-03/error.log
while executing
"try_catch openroad -exit $::env(SCRIPTS_DIR)/openroad/or_route.tcl |& tee $::env(TERMINAL_OUTPUT) $::env(fastroute_log_file_tag).log"
(procedure "global_routing" line 5)
invoked from within
"global_routing"
(procedure "run_routing" line 15)
invoked from within
"run_routing"
(procedure "run_non_interactive_mode" line 16)
invoked from within
"run_non_interactive_mode {*}$argv"
invoked from within
"if { [info exists flags_map(-interactive)] || [info exists flags_map(-it)] } {
puts_info "Running interactively"
if { [info exists arg_values(-file)..."
(file "./flow.tcl" line 164)
Any ideas what could be the problem... maybe Total Wirelengh shouldn't be negative?Anish
11/25/2020, 3:51 AMAnish
11/25/2020, 3:52 AMGitHub (Legacy)
11/25/2020, 6:58 AM./flow.tcl -design myproject
I get
Running Static Timing Analysis...
OpenSTA 2.2.0 0d73b5b65a Copyright (c) 2019, Parallax Software, Inc.
License GPLv3: GNU GPL version 3 <http://gnu.org/licenses/gpl.html>
Warning: /home/jcyr/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib, line 31 default_operating_condition ff_n40C_1v95 not found.
Warning: /home/jcyr/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib, line 32 default_operating_condition ss_100C_1v60 not found.
Error: cannot read file /openLANE_flow/openlane/designs/myproject/runs/25-11_06-35/results/synthesis/myproject.synthesis_optimized.v.
Looking at /home/jcyr/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib, we have:
default_leakage_power_density : 0.0000000000;
default_operating_conditions : "ff_n40C_1v95";
operating_conditions ("ff_n40C_1v95") {
voltage : 1.9500000000;
process : 1.0000000000;
temperature : -40.00000000;
tree_type : "balanced_tree";
}
power_lut_template ("power_inputs_1") {
Moving default_operating_conditions like such, and doing the same for /home/jcyr/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib:
default_leakage_power_density : 0.0000000000;
operating_conditions ("ff_n40C_1v95") {
voltage : 1.9500000000;
process : 1.0000000000;
temperature : -40.00000000;
tree_type : "balanced_tree";
}
default_operating_conditions : "ff_n40C_1v95";
power_lut_template ("power_inputs_1") {
Fixes the two warnings, but the missing /openLANE_flow/openlane/designs/myproject/runs/25-11_06-35/results/synthesis/*myproject.synthesis_optimized.v* error remains a show stopper. Any ideas why it isn't being created?
efabless/openlaneMatt Venn
11/25/2020, 10:08 AMMatt Venn
11/25/2020, 10:08 AMMatt Venn
11/25/2020, 10:08 AMMatt Venn
11/25/2020, 10:09 AMtnt
11/25/2020, 10:16 AMset ::env(SYNTH_DEFINES) "BLACKBOX"
in your config.tcl
should work if I read things correctly.Matt Venn
11/25/2020, 10:17 AMtnt
11/25/2020, 10:34 AMtnt
11/25/2020, 10:34 AMWarning: Cell sky130_fd_sc_hd__decap_6 has no pins
Note: Implicit pin (no pins)
Warning: Cell sky130_fd_sc_hd__decap_12 has no pins
Note: Implicit pin (no pins)
Warning: Cell sky130_fd_sc_hd__decap_12 has no pins
Note: Implicit pin (no pins)
Warning: Cell sky130_fd_sc_hd__decap_6 has no pins
Note: Implicit pin (no pins)
Warning: Cell sky130_fd_sc_hd__decap_12 has no pins
Note: Implicit pin (no pins)
Warning: Cell sky130_fd_sc_hd__decap_6 has no pins
Note: Implicit pin (no pins)
Warning: Cell sky130_fd_sc_hd__fill_1 has no pins
Note: Implicit pin (no pins)
Warning: Cell sky130_fd_sc_hd__decap_8 has no pins
Note: Implicit pin (no pins)
Warning: Cell sky130_fd_sc_hd__decap_8 has no pins
Note: Implicit pin (no pins)
Warning: Cell sky130_fd_sc_hd__fill_2 has no pins
Note: Implicit pin (no pins)
Warning: Cell sky130_fd_sc_hd__decap_8 has no pins
Note: Implicit pin (no pins)
tnt
11/25/2020, 10:34 AMtnt
11/25/2020, 10:34 AMtnt
11/25/2020, 10:35 AMtnt
11/25/2020, 10:35 AMMatt Venn
11/25/2020, 10:37 AMtnt
11/25/2020, 10:38 AMMatt Venn
11/25/2020, 10:42 AM