tnt
11/20/2020, 11:00 AMtnt
11/20/2020, 11:00 AMWajeh ul hasan
11/20/2020, 11:09 AMCell sky130_fd_sc_hd__o22a_4 couldn't be read
DEF read, Line 159 (Error): Cell sky130_fd_sc_hd__o22a_4 is not defined. Maybe you have not read the corresponding LEF file?
Cell sky130_fd_sc_hd__a2bb2o_4 couldn't be read
DEF read, Line 160 (Error): Cell sky130_fd_sc_hd__a2bb2o_4 is not defined. Maybe you have not read the corresponding LEF file?
Cell sky130_fd_sc_hd__xor2_4 couldn't be read
DEF read, Line 161 (Error): Cell sky130_fd_sc_hd__xor2_4 is not defined. Maybe you have not read the corresponding LEF file?
Cell sky130_fd_sc_hd__inv_8 couldn't be read
DEF read, Line 162 (Error): Cell sky130_fd_sc_hd__inv_8 is not defined. Maybe you have not read the corresponding LEF file?
Cell sky130_fd_sc_hd__inv_8 couldn't be read
DEF read, Line 163 (Error): Cell sky130_fd_sc_hd__inv_8 is not defined. Maybe you have not read the corresponding LEF file?
Cell sky130_fd_sc_hd__and2_4 couldn't be read
DEF read, Line 164 (Error): Cell sky130_fd_sc_hd__and2_4 is not defined. Maybe you have not read the corresponding LEF file?
And the list goes on..
Which LEF is it referring to?
The merged.lef
has these cells included in it.
I get the same message when I ran spm
design as well.tnt
11/20/2020, 11:12 AM.lef
before loading the .def
?tnt
11/20/2020, 11:13 AM.drc.mag
use the -dereference
optiontnt
11/20/2020, 11:13 AMPhilipp Gühring
11/20/2020, 9:15 PMaryap
11/20/2020, 9:16 PMtgingold
11/20/2020, 9:22 PMPhilipp Gühring
11/20/2020, 9:24 PMtgingold
11/20/2020, 9:32 PMPhilipp Gühring
11/20/2020, 10:10 PMPhilipp Gühring
11/20/2020, 10:12 PMaryap
11/20/2020, 10:15 PMpower_pins ""
but then it complains that not all power/ground ports were found:
Warning: No pins in the LEF view of switches\[0\].elem.es.impl marked for use as power
Warning: Attempting to match power pin by name (using top-level port name) for cell: switches\[0\].elem.es.impl
Warning: No pins in the LEF view of switches\[0\].elem.es.impl marked for use as ground
Warning: Attempting to match ground pin by name (using top-level port name) for cell: switches\[0\].elem.es.impl
Warning: not all power pins found for cell: switches\[0\].elem.es.impl
Exiting... Use --ignore-missing-pins to ignore such errors
tnt
11/20/2020, 10:17 PMaryap
11/20/2020, 10:18 PM/openLANE_flow/scripts/write_powered_def.py
aryap
11/20/2020, 10:20 PM--ignore-missing-pins
flag into scripts/lvs.tcl
Philipp Gühring
11/20/2020, 10:59 PMPhilipp Gühring
11/20/2020, 10:59 PM[ERROR] RePlAce diverged at initial iteration.
Please tune the parameters again (REPL-5)
Is there an easy solution for this?GitHub (Legacy)
11/21/2020, 11:28 AMTroy Benjegerdes
11/21/2020, 9:11 PMaryap
11/21/2020, 9:13 PMTroy Benjegerdes
11/21/2020, 9:20 PMtnt
11/21/2020, 10:03 PMKevin Baragona
11/21/2020, 10:42 PMKevin Baragona
11/21/2020, 10:42 PMKevin Baragona
11/22/2020, 12:16 AMSimon
11/22/2020, 8:37 AMtnt
11/22/2020, 2:47 PMtnt
11/22/2020, 2:48 PM