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  • t

    tnt

    11/17/2020, 2:19 PM
    DRC done ...
    Copy code
    DRC style is now "drc(full)"
Loading DRC CIF style.
[INFO]: COUNT: 25423759
  • t

    tnt

    11/17/2020, 2:19 PM
    Copy code
    Circuit 1 contains 4942 devices, Circuit 2 contains 4942 devices.
Circuit 1 contains 3194 nets,    Circuit 2 contains 3128 nets. *** MISMATCH ***
  • t

    tnt

    11/17/2020, 2:19 PM
    Copy code
    Number of pins violated: 50
Number of nets violated: 41
  • t

    tnt

    11/17/2020, 2:19 PM
    None of that looks good though.
    😞 1
  • i

    ibad1112

    11/17/2020, 6:54 PM
    @User There are several gds files in the caravel repository. Do we have to merge them all and then open them in magic. Also what is the process of streaming in and out of gds
  • g

    GitHub (Legacy)

    11/17/2020, 7:03 PM
    #91 libs.ref/sky130_fd_io/verilog/sky130_fd_io.v missing Issue closed by mballance efabless/openlane
  • t

    tnt

    11/17/2020, 7:03 PM
    Are 
    netgen
    results not saved ?
  • t

    tnt

    11/17/2020, 7:04 PM
    nm, ... name in logs is 
    lvs
    not 
    netgen
  • t

    tnt

    11/17/2020, 7:17 PM
    So ... how does one go about fixing LVS mismatches ?
  • i

    ibad1112

    11/17/2020, 7:57 PM
    @User There are several gds files in the caravel repository. Do we have to merge them all and then open them in magic. Also what is the process of streaming in and out of gds
  • t

    tnt

    11/17/2020, 8:05 PM
    Ah, running DRC on DEF/LEF returns 131 violations, so that's more manageable. (and explains LVS mismatch).
    ✔️ 1
  • a

    aryap

    11/17/2020, 8:20 PM
    I get a lot of 
    X overlap Y
    errors from opendp, before it exist "abnormally" and kills the flow. Is there any received wisdom on how to avoid this? 
    FP_CORE_UTIL
    is 10 and 
    PL_TARGET_DENSITY
    is 0.25
    t
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  • a

    aryap

    11/17/2020, 8:21 PM
    *exits
  • t

    tnt

    11/17/2020, 9:45 PM
  • t

    tnt

    11/17/2020, 9:45 PM
    That's the current state that should reproduce those weird antennas.
  • m

    mehdi

    11/17/2020, 9:48 PM
    Thanks @User, Can you share a DEF + script to replicate the issue ?
    t
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  • d

    drr

    11/17/2020, 10:02 PM
    Still stuck on this tritonRoute issue, it's always immediately before 
    start track assignment
    . There is no useful context in the logs, just the console logs before it is killed. I doubt it is OoM as the docker process peaks at about 3.8GB and there is a lot of vacant memory to use. Does anyone have advice on how to figure out the root cause, or potential causes for this? I'll reply in a thread with more context
    t
    m
    • 3
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  • d

    drr

    11/17/2020, 10:04 PM
    typo: I meant to say "immediately after `start track assignment`"
  • t

    tnt

    11/18/2020, 8:11 AM
    I tried 
    DIODE_INSERTION_STRATEGY
    set to 
    0
    . I was possibly expecting some Antenna errors, but instead what I got is a bunch of 
    All nwells must contain metal-connected N+ taps (nwell.4)
    DRC errors. Looks like disabling diodes also disabled tap cells ?!?
    a
    • 2
    • 17
  • w

    Wajeh ul hasan

    11/18/2020, 10:34 AM
    Hello, what is the difference between 
    global_placement_or
    and 
    global_placement
    Similarly, 
    detailed_placement_or and detailed_placement
    It is written that one uses Replace and OpenDP while the other uses openroad. But the openroad also uses Replace and OpenDP, so what's the difference between the 2? @User @User I was running the interactive mode in which 
    detailed_placement
    errored out while the 
    detailed_placement_or
    ran successfully.
    t
    • 2
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  • w

    Wajeh ul hasan

    11/18/2020, 10:38 AM
    This is the snippet of def file after 
    cts
    stage. The design is 
    spm
    . It seemed as if the cells are overlapping each other. This looks more like global placement, shouldn't 
    detailed_placement
    put the cells neatly in the rows with zero overlap?
    cts.def
    😁 1
    💯 1
    ✔️ 1
    🎉 1
    t
    • 2
    • 2
  • w

    Wajeh ul hasan

    11/18/2020, 10:47 AM
    Is it possible to use some other synthesizer and incorporate the netlist in the openlane flow. If yes then what would be the procedure. I mean something like: 1. 
    prep -design
    2. skipping 
    run_synthesis
    [Here can I put the generated netlist in 
    runs/result/synthesis
    and go on with the floorplan?] or 
    run_synthesis
    generates some temporary files which are need for the successive stage 3. 
    run_floorplan
    and so on
    a
    • 2
    • 2
  • m

    Matt Venn

    11/18/2020, 10:50 AM
    I created a #caravel channel
  • g

    GitHub (Legacy)

    11/18/2020, 2:59 PM
    #93 Design Always Fails Synthesis after Updating to Develop Issue closed by agorararmard efabless/openlane
  • g

    GitHub (Legacy)

    11/18/2020, 5:50 PM
    #96 manual_macro_place.py: allow comments in the config file Pull request opened by tgingold Also discard empty lines. efabless/openlane Travis CI: Build Created
  • t

    tnt

    11/18/2020, 5:57 PM
    So ... power is not routed to the macros I'm using, do I have to do something special ?
  • t

    tgingold

    11/18/2020, 6:03 PM
    I have just asked a similar question in the caravel channel
  • t

    tgingold

    11/18/2020, 6:28 PM
    @User I have two problems with macros: more DRC problems and power not connected (which doesn't help LVS). Is it the same for you ?
  • t

    tnt

    11/18/2020, 6:30 PM
    Well, the macro I'm using is a SRAM that doesn't obey drc rules so ... I get tens of thousands of DRC errors if I check the GDS ... I resorted to 
    MAGIC_DRC_USE_GDS
    set to 
    0
    but I still get DRC errors although they don't seem to be related to the macro really.
  • t

    tnt

    11/18/2020, 6:30 PM
    And yeah, power isn't connected.
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