GitHub (Legacy)
11/05/2020, 11:40 PMmake test
failure on rc4
Issue opened by jeras
I First tried openlane rc3 last week, I was able to install all dependencies and to add myself to the docker group.
I was able to run make test
without issues. This is on Ubuntu 20.04.
Today I tried rc4
twice, the second time with a thorough cleanup (not sure about docker).
make test
ends with the next message:
[INFO]: /openLANE_flow/designs/spm/runs/openlane_test/results/magic/spm.spice against /openLANE_flow/designs/spm/runs/openlane_test/results/lvs/spm.lvs.powered.v
[INFO]: Running Antenna Checks...
[INFO]: Running OpenROAD Antenna Rule Checker...
[INFO]: Generating Final Summary Report...
[SUCCESS]: Flow Completed Without Fatal Errors.
/bin/sh: 1: [[: not found
Basic test failed
efabless/openlaneGitHub (Legacy)
11/06/2020, 10:56 AMGitHub (Legacy)
11/06/2020, 2:16 PMGitHub (Legacy)
11/06/2020, 2:17 PMAmr Gouhar
11/06/2020, 2:24 PMAmr Gouhar
11/06/2020, 2:29 PMGitHub (Legacy)
11/06/2020, 2:29 PMissues
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11/06/2020, 8:22 PMGitHub (Legacy)
11/08/2020, 6:25 PMinverter
to try running a spice simulation.
The generated spice file was designs/inverter/runs/07-11_21-11/results/magic/inverter.spice
.
I expected a full parasitic extraction netlist, but I am actually more happy with what I got, which is a netlist of standard cells (including capacitors filler and tap cells).
After I tried to create an example simulation and I got the next error.
Error: too few nodes: xfiller_0_15 vgnd vpwr sky130_fd_sc_hd__decap_12
The affected line in the spice netlist is:
XFILLER_0_15 VGND VPWR sky130_fd_sc_hd__decap_12
The problem seems two missing connections for ports VNB
& VPB
for a decap
cell.
.subckt sky130_fd_sc_hd__decap_12 VGND VNB VPB VPWR
M1000 VPWR VGND VPWR VPB phighvt w=870000u l=4.73e+06u
+ ad=4.524e+11p pd=4.52e+06u as=0p ps=0u
M1001 VGND VPWR VGND VNB nshort w=550000u l=4.73e+06u
+ ad=2.86e+11p pd=3.24e+06u as=0p ps=0u
.ends
The same ports are also present on filler cells and also not connected in the netlist.
.subckt sky130_fd_sc_hd__fill_1 VGND VNB VPB VPWR
.ends
Interestingly, sub-circuit instances are also not named consistently.
XFILLER_*_*
is used for decap
and fill
cells, some instances use the XPHY_*
name.
efabless/openlaneGitHub (Legacy)
11/08/2020, 6:58 PMmake test
failure on rc4
Issue closed by jeras
efabless/openlaneGitHub (Legacy)
11/08/2020, 8:06 PMmake regression
will crash.
<prompt>:openlane <user>$ make regression
cd <local_dir> && \
docker run -it -v <local_dir>:/openLANE_flow -v <local_dir>:<local_dir> -e PDK_ROOT=<pdk_dir> -u 501:20 efabless/openlane:rc4 sh -c "python3 run_designs.py -dts -tar logs reports -html -t TEST_SW_HD -th 4 -p 0"
Traceback (most recent call last):
File "run_designs.py", line 346, in <module>
design_name= utils.get_design_name(design, config)
File "/openLANE_flow/scripts/utils/utils.py", line 55, in get_design_name
config_file_opener = open(config_file, "r")
FileNotFoundError: [Errno 2] No such file or directory: '/openLANE_flow/./designs/biriscv_tcm//config.tcl'
make: *** [regression] Error 1
Maybe change get_design_name
in scripts/utils/utils.py
to something like
try:
config_file_opener = open(config_file, "r")
configs = config_file_opener.read()
config_file_opener.close()
except FileNotFoundError:
print ("{design} is missing its config file!".format(design=design))
return "INVALID DESIGN PATH"
efabless/openlaneAireen Amir Jalal
11/09/2020, 5:42 AMWajeh ul hasan
11/09/2020, 5:57 PM10.1.2. Re-integrating ABC results.
[ERROR]: during executing: "yosys -c /openLANE_flow/scripts/synth.tcl -l /openLANE_flow/designs/design_top/runs/first_run/logs/synthesis/yosys.log |& tee >&@stdout"
[ERROR]: Exit code: 1
[ERROR]: Last 10 lines:
child killed: kill signal
tnt
11/09/2020, 8:19 PMtnt
11/09/2020, 8:20 PMtnt
11/09/2020, 8:22 PMtnt
11/09/2020, 10:04 PMGitHub (Legacy)
11/10/2020, 4:05 PMaryap
11/10/2020, 6:00 PMGitHub (Legacy)
11/10/2020, 6:14 PMGitHub (Legacy)
11/10/2020, 6:15 PMWajeh ul hasan
11/11/2020, 5:31 AMMACRO sky130_fd_sc_hd__dfxtp_4
CLASS CORE ;
FOREIGN sky130_fd_sc_hd__dfxtp_4 ;
ORIGIN 0.000000 0.000000 ;
SIZE 8.740000 BY 2.720000 ;
SYMMETRY X Y R90 ;
SITE unithd ;
And this is from the generated merged.lef
MACRO sky130_fd_sc_hd__dfxtp_4
CLASS CORE ;
FOREIGN sky130_fd_sc_hd__dfxtp_4 ;
ORIGIN 0.000000 0.000000 ;
SIZE 12.42 BY 2.72 ;
SYMMETRY X Y R90 ;
SITE unithd ;
GitHub (Legacy)
11/11/2020, 2:12 PMGitHub (Legacy)
11/11/2020, 2:28 PMWajeh ul hasan
11/11/2020, 5:05 PMAnson
11/12/2020, 2:32 AMsky130_fd_sc_hd__fa
module instantiated in a verilog file and it works with Verilator, but when trying to synthesize Openlane is having trouble finding the module. I've also tried to include skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/fa/*.v
as both Verilog or Blackbox verilog files within config.tcl
, but I end up getting a syntax error in another file (error in thread to keep this short). Is there a proper way to get this working? (Note: I am using rc2)GitHub (Legacy)
11/12/2020, 6:18 PMGitHub (Legacy)
11/12/2020, 6:52 PMPhilipp Gühring
11/12/2020, 10:58 PMRiking28
11/12/2020, 11:25 PM