16. Executing ABC pass (technology mapping using ABC).

16.1. Extracting gate netlist of module `\mac_cluster' to `/tmp/yosys-abc-ScuQlb/input.blif'..
Extracted 11382 gates and 11705 wires to a netlist network with 323 inputs and 384 outputs.

16.1.1. Executing ABC.
ERROR: Can't open ABC output file `/tmp/yosys-abc-ScuQlb/output.blif'.

989 ABC: ** cmd error: aborting 'source /tmp/yosys-abc-uhjRHz/abc.script'
990 ABC: node 9893 has no fanout

config.tcl

[INFO]: 
      ___   ____   ___  ____   _       ____  ____     ___
     /   \ |    \ /  _]|    \ | |     /    ||    \   /  _]
    |     ||  o  )  [_ |  _  || |    |  o  ||  _  | /  [_
    |  O  ||   _/    _]|  |  || |___ |     ||  |  ||    _]
    |     ||  | |   [_ |  |  ||     ||  _  ||  |  ||   [_
     \___/ |__| |_____||__|__||_____||__|__||__|__||_____|


[INFO]: Version: rc3
[INFO]: Running non-interactively
[INFO]: Using design configuration at /openLANE_flow/designs/spm/config.tcl
[INFO]: PDKs root directory: /home/konstantinos/vlsi/pdks
[INFO]: PDK: sky130A
[INFO]: Standard Cell Library: sky130_fd_sc_hd
mergeLef.py : Merging LEFs
sky130_fd_sc_hd.lef: SITEs matched found: 0
sky130_fd_sc_hd.lef: MACROs matched found: 437
mergeLef.py : Merging LEFs complete
padLefMacro.py : Padding technology lef file
Derived SITE width (microns): 0.46
Derived SITE height (microns): 5.44
Right cell padding (microns): 3.68
Left cell padding (microns): 0.0
Top cell padding (microns): 0.0
Bottom cell padding (microns): 0.0
Skipping LEF padding for MACRO  sky130_fd_sc_hd__decap_12
Skipping LEF padding for MACRO  sky130_fd_sc_hd__decap_3
Skipping LEF padding for MACRO  sky130_fd_sc_hd__decap_4
Skipping LEF padding for MACRO  sky130_fd_sc_hd__decap_6
Skipping LEF padding for MACRO  sky130_fd_sc_hd__decap_8
Skipping LEF padding for MACRO  sky130_fd_sc_hd__fill_1
Skipping LEF padding for MACRO  sky130_fd_sc_hd__fill_2
Skipping LEF padding for MACRO  sky130_fd_sc_hd__fill_4
Skipping LEF padding for MACRO  sky130_fd_sc_hd__fill_8
Skipping LEF padding for MACRO  sky130_fd_sc_hd__tap_1
Skipping LEF padding for MACRO  sky130_fd_sc_hd__tap_2
Skipping LEF padding for MACRO  sky130_fd_sc_hd__tapvgnd_1
Skipping LEF padding for MACRO  sky130_fd_sc_hd__tapvgnd2_1
Skipping LEF padding for MACRO  sky130_fd_sc_hd__tapvpwrvgnd_1
padLefMacro.py : Finished
[ERROR]: during executing: "/openLANE_flow/scripts/libtrim.pl /home/konstantinos/vlsi/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib /home/konstantinos/vlsi/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd/no_synth.cells > /openLANE_flow/designs/spm/runs/25-10_10-25/tmp/trimmed.lib"
[ERROR]: Last 10 lines:
child killed: segmentation violation

[ERROR]: Please check /openLANE_flow/scripts/libtrim.pl  log file
[ERROR]: Dumping to /openLANE_flow/designs/spm/runs/25-10_10-25/error.log

    while executing
"try_catch $::env(SCRIPTS_DIR)/libtrim.pl $arg_values(-input) $scl_no_synth_lib > $arg_values(-output)"
    (procedure "trim_lib" line 14)
    invoked from within
"trim_lib"
    (procedure "prep" line 176)
    invoked from within
"prep {*}$args"
    (procedure "run_non_interactive_mode" line 9)
    invoked from within
"run_non_interactive_mode {*}$argv"
    invoked from within
"if { [info exists flags_map(-interactive)] || [info exists flags_map(-it)] } {
    puts_info "Running interactively"
    if { [info exists arg_values(..."
    (file "./flow.tcl" line 160)

<https://github.com/efabless/openlane/blob/master/doc/chip_integration.md>

set ::env(VERILOG_FILES_BLACKBOX) $::env(OPENLANE_ROOT)/designs/memory_core/src/sram.v
set ::env(SYNTH_READ_BLACKBOX_LIB) 1

src

memory_core.v

core.v

sram.v

memory_core

module memory_core(clk, reset);
          input clk;
          input reset;
endmodule

Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module memory_core:
created 0 $alu and 0 $macc cells

Creating internal representation of mux trees.
No muxes found in this module.
Removed 0 multiplexer ports.

Extracting gate netlist of module `\memory_core' to `/tmp/yosys-abc-BDpQ39/input.blif'..
Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs.
Don't call ABC as there is nothing to map

~/scripts/tcl_commands/floorplan.tcl

set <filename> [open $::env(verilog2def_report_file_tag).core_area.rpt]

gen_pdn

/openLANE_flow/designs/brqrv_core/src/brqrv_core.sv:16: ERROR: syntax error, unexpected TOK_PARAMETER

15 module brqrv_core (

16     parameter bit                 PMPEnable        = 1'b0,

17     parameter int unsigned        PMPGranularity   = 0,