open-source-silicon #openlane

2 new commits pushed to `develop` `c993a0a2` - configuration/README.md: fix a typo `f67195b9` - Merge pull request #76 from tgingold/fix-typo-readme efabless/openlane

GitHub (Legacy)

10/16/2020, 8:15 PM

#77 add s44 LUT design Pull request opened by growly This is a tiny design, and it doesn't work, but we'd very much like it to. efabless/openlane Travis CI: Build Created

Mitch Bailey

10/19/2020, 9:33 AM

I noticed that the test design picorv32a has buffers with no input. Is this known and intentional? Hi-Z input to inverters is generally not a good thing. Here's a sample from the powered verilog used for LVS. designs/picorv32a/runs/*/results/lvs/picorv32a.lvs.powered.v

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sky130_fd_sc_hd__buf_2 _31169_ (
  .A(mem_la_wdata[7]),
  .VGND(VGND),
  .VPWR(VPWR),
  .X(pcpi_rs2[7])
 );
 sky130_fd_sc_hd__buf_2 _31170_ (
  .VGND(VGND),
  .VPWR(VPWR),
  .X(trace_data[0])
 );34
 sky130_fd_sc_hd__buf_2 _31171_ (
  .VGND(VGND),
  .VPWR(VPWR),
  .X(trace_data[1])
 );

31169 is as expected - input 'A' has a net assigned. However, 31170, 31171, and 34 other instances are missing connections to the buffer input 'A'. This appears to lead to a floating input in the final layout.

GitHub (Legacy)

10/19/2020, 12:05 PM

1 new commit pushed to `develop` `9759c3e8` - Update openroad (last one before switch to master) efabless/openlane

GitHub (Legacy)

10/19/2020, 2:18 PM

1 new commit pushed to `develop` `3ad4e7f4` - workaround FR caveats with designs bigger than 10K cells efabless/openlane

GitHub (Legacy)

10/19/2020, 2:20 PM

1 new commit pushed to `develop` `0882565d` - Tie undefs to zero before hilomapping efabless/openlane

GitHub (Legacy)

10/19/2020, 6:01 PM

2 new commits pushed to `develop` `867b39f1` - default max diode ins iters to 1 `306836f7` - removing 2 deprecated pin reordering scripts efabless/openlane

GitHub (Legacy)

10/19/2020, 7:24 PM

5 new commits pushed to `develop` `e41b478f` - add 151 (UC Berkeley CS 151/251A class) design `8e926700` - an S44 LUT `ced7c255` - merge upstream `dd2ec94f` - add Amr's working config.tcl; fix use of ^ as exponent `69b366c4` - Merge pull request #77 from growly/develop efabless/openlane

GitHub (Legacy)

10/19/2020, 7:24 PM

#77 add s44 LUT design Pull request merged by agorararmard efabless/openlane

GitHub (Legacy)

10/19/2020, 7:49 PM

1 new commit pushed to `develop` `50c90c04` - perform parasitic estimation after global placement and before optimizations efabless/openlane

GitHub (Legacy)

10/20/2020, 7:07 AM

#78 rc3: OpenPhySyn Segmentation Fault Issue opened by aunali1 Fresh setup of PDKs and OpenLane rc3. Using

sky130_fd_sc_hdll

library. Ran the simple

./flow.tcl -design spm

and got the following:

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[OpenPhySyn] [2020-10-20 07:05:51.834] [info] Invoking repair_timing transform
[OpenPhySyn] [2020-10-20 07:05:51.840] [info] Buffer library: sky130_fd_sc_hdll__buf_4, sky130_fd_sc_hdll__buf_8, sky130_fd_sc_hdll__buf_1
[OpenPhySyn] [2020-10-20 07:05:51.840] [info] Inverter library: None
[OpenPhySyn] [2020-10-20 07:05:51.840] [info] Buffering: enabled
[OpenPhySyn] [2020-10-20 07:05:51.840] [info] Driver sizing: enabled
[OpenPhySyn] [2020-10-20 07:05:51.840] [info] Pin-swapping: enabled
[OpenPhySyn] [2020-10-20 07:05:51.840] [info] Mode: Timing-Driven
[OpenPhySyn] [2020-10-20 07:05:51.840] [info] Iteration 1
[ERROR]: during executing: "Psn /openLANE_flow/scripts/openPhySyn.tcl |& tee >&@stdout /openLANE_flow/designs/spm/runs/20-10_07-05/logs/placement/openphysyn.log"
[ERROR]: Last 10 lines:
child killed: segmentation violation

[ERROR]: Please check Psn  log file
[ERROR]: Dumping to /openLANE_flow/designs/spm/runs/20-10_07-05/error.log

    while executing
"try_catch Psn $::env(SCRIPTS_DIR)/openPhySyn.tcl |& tee $::env(TERMINAL_OUTPUT) $::env(openphysyn_log_file_tag).log"
    (procedure "run_openPhySyn" line 7)
    invoked from within
"run_openPhySyn"
    (procedure "run_placement" line 13)
    invoked from within
"run_placement"
    (procedure "run_non_interactive_mode" line 13)
    invoked from within
"run_non_interactive_mode {*}$argv"
    invoked from within
"if { [info exists flags_map(-interactive)] || [info exists flags_map(-it)] } {
    puts_info "Running interactively"
    if { [info exists arg_values(..."
    (file "./flow.tcl" line 160)

dmesg

reports the segfault as:

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[15672.622994] Psn[38572]: segfault at 18 ip 00000000008962cf sp 00007fff5f687630 error 4 cpu 4 in Psn[400000+15d6000]
[15672.623000] Code: 89 ef ff 50 10 4c 89 ef 84 c0 49 8b 45 00 0f 84 e7 00 00 00 ff 50 18 48 8b 7b 20 49 89 c7 48 8b 07 4c 89 fe ff 90 58 02 00 00 <48> 8b 78 18 49 89 c6 e8 f5 2d fb ff 48 8b 7b 48 4c 89 fe 84 c0 75

If it helps, host distro is Clear Linux. efabless/openlane

GitHub (Legacy)

10/20/2020, 2:19 PM

1 new commit pushed to `develop` `a2e0f5ad` - Update openroad efabless/openlane

GitHub (Legacy)

10/20/2020, 4:32 PM

2 new commits pushed to `develop` `724f579c` - SW_HDLL benchmark update (Oct. 16th) `caea969f` - testing the CI runtime on bigger designs efabless/openlane

Matt Venn

10/20/2020, 5:16 PM

I added this line to /openLANE_flow/scripts/synth.tcl : show -prefix post_techmap and show -prefix post_synth

GitHub (Legacy)

10/20/2020, 7:28 PM

#78 rc3: OpenPhySyn Segmentation Fault Issue closed by agorararmard efabless/openlane

Anish

10/21/2020, 2:59 AM

anyone ever hit a

Anish

10/21/2020, 2:59 AM

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Error: or_ioplacer.tcl, 44 invalid command name "ioPlacer::set_min_distance"

Anish

10/21/2020, 2:59 AM

with openlane?

Anish

10/21/2020, 3:00 AM

(latest master branch)

Anish

10/21/2020, 3:04 AM

Hitting the same problem both with a design that used to work, as well as with a brand new very simple design

GitHub (Legacy)

10/21/2020, 3:15 AM

#71 Update chip_integration.md Pull request closed by growly efabless/openlane

GitHub (Legacy)

10/21/2020, 1:15 PM

1 new commit pushed to `develop` `1313b03c` - [CI]: test the log-limit-exceeded designs without live log efabless/openlane

GitHub (Legacy)

10/21/2020, 3:48 PM

1 new commit pushed to `develop` `81fa2ded` - summary report generation enhancement efabless/openlane

Wajeh ul hasan

10/21/2020, 7:26 PM

Hello, I was going through the

chip integration

section on github and many links mentioned there are dead. The documentation says it is under development but the last update was around a month ago. Any updates about it? https://github.com/efabless/openlane/blob/master/doc/chip_integration.md#power-routing

Wajeh ul hasan

10/22/2020, 11:59 AM

Hello, I was running the design with the memory module set as a black_box by adding the below two variables in the `config.tc`l script:

set ::env(VERILOG_FILES_BLACKBOX) $::env(OPENLANE_ROOT)/designs/design_name/src/abc.v

set ::env(SYNTH_READ_BLACKBOX_LIB) 1

However, after synthesis I realized that although there were no errors but no mapping was done and an empty netlist was generated. I went through the log files and observed that it is not creating anything. It had the following the messages:

Executing ALUMACC pass (create $alu and $macc cells).

Extracting $alu and $macc cells in module memory_core:

created 0 $alu and 0 $macc cells

Creating internal representation of mux trees.

No muxes found in this module.

Removed 0 multiplexer ports.

`Extracting gate netlist of module `\memory_core' to

/tmp/yosys-abc-BDpQ39/input.blif'..

Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs.

Don't call ABC as there is nothing to map

Matt A

10/22/2020, 12:59 PM

Using the openlane docker environment, what is considered a successful flow (e.g., ./flow.tcl -design xtea)? Using the xtea design as an example, I see it has negative slack (timing errors), but tritonRoute.drc is empty which I'm assuming means no drc errors. What other possible errors should I look for?

GitHub (Legacy)

10/22/2020, 1:41 PM

2 new commits pushed to `develop` `77eade61` - SW_HD benchmark update (Oct. 20th) `e36fdedd` - minor CI updates efabless/openlane

GitHub (Legacy)

10/22/2020, 2:13 PM

2 new commits pushed to `develop` `25ef9e39` - PDK_STRUCTURE.md: fix typo. `ffc9bb60` - Merge pull request #44 from tgingold/typo-fix efabless/openlane

GitHub (Legacy)

10/22/2020, 2:13 PM

#44 PDK_STRUCTURE.md: fix typo. Pull request merged by agorararmard efabless/openlane