Has anyone tried doing the parasitic extraction of gds generated from openlane in cadence virtuoso ?

Hello everyone, I have completed the first multi-height RTL2GDS flow for mixed signal SoC. I am attaching the link to my GitHub repository. Do have a look😊 I would once again like to thank all of you for helping me out and @User for mentoring me. https://github.com/praharshapm/vsdmixedsignalflow

@User @User please check with @User @User as they reviewed the design and there are open questions about confirming supply connectivity.

2nd mile-stone in field open-source (efabless open-lane EDA + Google/Sky130 open-process). GitHub is indeed the new RESUME for VLSI industry. Again, let's take a backseat and appreciate/encourage all freshers like @User to do a similar kind of work, by congratulating them @User joined our research project group under VSD Research internship program which runs for 8-weeks. He was supposed to develop flow for standard cell design and characterization using all open-source tools - magic/ngspice, then plug those standard cells into open-source PNR flow by open-lane, and benchmark RTL2GDS flow results. This needed a knowledge, not only of PNR, but device physics, custom layout, DRC/LVS and then (finally) Physical design/STA. All of above using open-source RISC-V design (picorv32a) + open-source EDA tools (open-lane by efabless) + open-process (google+skywater130nm). Here's detailed masterpiece of his work. Its open for review/critics/feedback/comments/usage and everything. Thanks again @User @User @User @User https://github.com/nickson-jose/vsdstdcelldesign

#29 Query for PnR Issue opened by rahulrvm82 Can we take any independent RTL to perform PnR? efabless/openlane

Is a RC3 planned soon wiht the pending improvements ?

I am working on porting the OSU 45nm Standard Cell Set (FreePDK) for Openlane. While trying to run the flow for the simple example design 'spm', I am encountering the following error during pin access in routing. Error: no ap for clkbuf_0_clk/A Error: no ap for clkbuf_0_clk/Y complete 56 pins Error: pin does not have access point Error: pin does not have access point complete 25 unique inst patterns @@@ dead end inst @@@ dead end inst Error: valid access pattern combination not found. I am also unable to reduce the no. of DRC violations during routing below 2 in spite of using TR14 strategy and a low FP_CORE_UTIL and PL_TARGET_DENSITY. The no. of such errors and DRC violations increases with the complexity of the design. Any idea how to go about solving this issue?

#30 Problem installing PDK in MAC Issue opened by bsrinath10 Dear Sir, I tried installing the OPENLANE in my Mac OS. I tried installing the SkyWater PDK . I am facing the following issue given in the attachment. Kindly help me for successful installation . with regards Srinath efabless/openlane

#29 Query for PnR Issue closed by ax3ghazy efabless/openlane

I'm encountering a huge negative slack (wns and tns) violation at the end of synthesis as reported by OpenSTA. When I checked the timing reports generated, it was clearly evident that the timing paths (max : recovery check) starting from the RST_N port caused the violations. One such example is as shown below: Startpoint: RST_N (input port clocked by vclk) Endpoint: 320257 (recovery check against rising-edge clock vclk) Path Group: async_default Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock vclk (rise edge) 0.00 0.00 clock network delay (ideal) 6.00 6.00 ^ input external delay 19.26 25.26 ^ RST_N (in) 0.00 25.26 ^ _320257_/RESET_B (sky130_fd_sc_hd__dfrtp_4) 25.26 data arrival time 12.00 12.00 clock vclk (rise edge) 0.00 12.00 clock network delay (ideal) 0.00 12.00 clock reconvergence pessimism 12.00 ^ _320257_/CLK (sky130_fd_sc_hd__dfrtp_4) -10.71 1.29 library recovery time 1.29 data required time --------------------------------------------------------- 1.29 data required time -25.26 data arrival time --------------------------------------------------------- -23.97 slack (VIOLATED) One possible way to fix the issue is by increasing the period of 'vclk'. I would like to know whether this is legal or should the period of vclk be fixed? Correct me if I'm wrong.

In the latest talk @User spoke about strive, and being able to connect the cpu to memory blocks. Can openlane handle multiple blocks now?

hi everyone. do we have ram macros yet?

unclear from a search of "RAM" in here. and the docs. and none of the designs openlane ships with seems to use anything but verilator models

from @User's post in #sky130 it looks like, maybe not yet?

We are experimenting and putting together a flow with osu180nm and magic/ngspice to plug in all custom cells into OpenRAM. Once that works (we made some progress just last night) and we have a solid flow, we will move to sky130 models. So we haven't moved our designs yet to sky130, but not sure if somebody else did

ah gotcha. good work!

@User It should be real soon now

#31 openLANE/efabless Issue opened by chandni0760 Hello I am Unable to clone the skywater-pdk using the following command; git clone https://github.com/google/skywater-pdk efabless/openlane

Hi, I have an issue using the openlane flow. TritonRoute reports these errors:

start pin access

 

complete 100 pins

Error: no ap for clkbuf_3_3_0_clk_i/A

Error: no ap for clkbuf_3_3_0_clk_i/X

Error: no ap for clkbuf_4_8_0_clk_i/A

Error: no ap for clkbuf_4_8_0_clk_i/X

Error: no ap for clkbuf_4_9_0_clk_i/A

Error: no ap for clkbuf_4_9_0_clk_i/X

Error: no ap for clkbuf_3_4_0_clk_i/A

Error: no ap for clkbuf_3_4_0_clk_i/X

Error: no ap for clkbuf_4_0_0_clk_i/A

The flow doesn't stop but it fails later. These buffers are added by TritonCTS, so I suppose the issue is either in cts, or in TritonRoute or in the library.

Any hint to narrow down this issue ? Did I make an obvious mistake ?

i'm getting

[ERROR] FastRoute cannot handle very congested design

. The design itself isn't that complicated, it's a simple RISC-V core from a 1-semester class. Perhaps the floorplan is too tight? Haven't found much through searches. Anyone else run into this?

6th mile-stone in field of open-source (efabless open-lane EDA + Google/Sky130 open-process) - This time for *VLSI fresher*s aiming to become VLSI & SoC designers A full-fledged video lectures on step-by-step process to install OpenLANE EDA tool chain and Sky130 PDK open-process on your own laptop, from scratch. There is a dependency on vsdflow though for fresh users and with Windows or fresh Unix machine. To do something like this, it needs a clear focus on end vision (can't share much details now), with very good VLSI fundamentals, which demands hours of efforts every day. Let's again take a back-seat and congratulate @User for this amazing online course. As mentioned sometime back, @User had joined our VSD Research IP design Internship group 8-weeks back along with 20 other participants. The day @User joined, he put everyday close to 12-14hours on given tasks and his results speaks for him Here's the link to the full video course (vsdflow is available separately, google search please :)): Watch it to observe all minute details being captured. Re-iterating - this is only for freshers, as VSD goal is to make sure every engineer on this planet, wanting to learn VLSI and SoC design, should not be deprived of right resources and intuitive learning methods https://www.udemy.com/course/vsd-a-complete-guide-to-install-openlane-and-sky130nm-pdk/ Also wait for next announcements - time for analog

#28 error during placement stage Issue closed by agorararmard efabless/openlane

#27 Cannot install via docker method on branch

develop

Issue closed by agorararmard efabless/openlane

#17 Error during the Synthesis Step Issue closed by agorararmard efabless/openlane

#32 Develop antenna or Pull request opened by agorararmard Integration of OR ARC controlled by $::env(USE_ARC_ANTENNA_CHECK) efabless/openlane License Compliance: 3 issues found Travis CI: Build Created Travis CI: Build Created Travis CI: Build Created Travis CI: Build Created ✅ No checks have passed 0/5 successful checks

#33 Overlap check failed during diode auto-placement Issue opened by kdp1965 Hi All, I am working on a 16-Bit processor I wrote many years ago (named Pico16) using the OpenLane flow. I am using the Docker image (downloaded last week) and have been able to get it all the way through the flow several times. I have also been able to get a couple of the examples to run. I am making a few extensions to my Pico16 processor ISA, and occasionally when I run "flow.tcl -design pico16", I get the following error (followed by some python error messages):

Warning: Overlap check failed (2).
 PHY_470 overlaps PHY_1
 PHY_4877 overlaps PHY_429
[ERROR]: during executing: "openroad -exit /openLANE_flow/scripts//openroad/or_diodes.tcl |& tee >&@stdout /openLANE_flow/designs/pico16/runs/04-09_19-06//logs//placement/diodes.log"
[ERROR]: Last 10 lines:
child process exited abnormally

[ERROR]: Please check openroad  log file
[ERROR]: Dumping to /openLANE_flow/designs/pico16/runs/04-09_19-06//error.log

Is this a known issue with a possible workaround? Thanks, Ken efabless/openlane

#33 Overlap check failed during diode auto-placement Issue closed by agorararmard efabless/openlane

is there a troubleshooting playbook yet?