Hey guys, do you have any tips on dealing with routing congestion problems? I am attaching the error I am getting. As a bit of context I am trying to harden a very simple SoC, which consists of 2 1-kbyte SRAM blocks and a simple risc-v core. I am also attaching the config.tcl file. Any help is appreciated.

Hello, do you know how to set the horizontal stripe (met5) for vccd1/vssd1 only and remove the others (vccd2, vdda1,2, vssd2, vssa1,2) but still keep them all at the power rings (to pass the XOR check)? Thanks

Hello, has anyone tried synthesizing an asynchronous design using openlane? In my case, openlane hangs at report_power. If I disable the power report( by commenting it out in sta.tcl ) it then hangs when generating the PDN. I have tried the following workaround, but it doesn't seem to change anything (https://github.com/The-OpenROAD-Project/OpenLane/issues/64). The rtl simulation works fine. Link to the openlane script: https://github.com/6Kotnk/caravel_example/blob/test/openlane/user_project_wrapper/config.tcl Any help would be appreciated.

Is there any simple way to see logic cell utilization reports of previous MPW projects from their github repos? I looked up some projects and try to find logic cell utilization reports but couldn't be able to accomplish anything?

hi all - what is the relationship of config.json to config.tcl? (e.g here https://github.com/efabless/caravel_user_project/tree/main/openlane/user_proj_example). what part of the flow uses config.json?

Can someone please help with the following IO placement error? I am trying to instantiate a picorv32 core with 1 SRAM that are both hardened individually as macros. Is there a limit on the number of I/O pins? I do not see this issue when I try the flow with the vanilla picorv32a design, which also has a lot of I/O pins.

[INFO]: Running IO Placement...
OpenROAD 8d53e9b018dec98fa63e907ddeb6c5406f035361
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0222] Reading LEF file: /openlane/designs/picorv32_sram/runs/RUN_2022.03.18_15.23.42/tmp/merged.lef
[INFO ODB-0223]     Created 13 technology layers
[INFO ODB-0224]     Created 25 technology vias
[INFO ODB-0225]     Created 443 library cells
[INFO ODB-0226] Finished LEF file:  /openlane/designs/picorv32_sram/runs/RUN_2022.03.18_15.23.42/tmp/merged.lef
[INFO ODB-0127] Reading DEF file: /openlane/designs/picorv32_sram/runs/RUN_2022.03.18_15.23.42/tmp/floorplan/3-initial_fp.def
[INFO ODB-0128] Design: picorv32_sram
[INFO ODB-0130]     Created 341 pins.
[INFO ODB-0131]     Created 877 components and 6168 component-terminals.
[INFO ODB-0133]     Created 948 nets and 2516 connections.
[INFO ODB-0134] Finished DEF file: /openlane/designs/picorv32_sram/runs/RUN_2022.03.18_15.23.42/tmp/floorplan/3-initial_fp.def
Found 0 macro blocks.
Using 1u default distance from corners.
[INFO PPL-0007] Random pin placement.
[ERROR PPL-0072] Number of pins (341) exceed number of valid positions (174).
Error: ioplacer.tcl, 60 PPL-0072
[ERROR]: during executing openroad script /openlane/scripts/openroad/ioplacer.tcl
[ERROR]: Exit code: 1
[ERROR]: Last 10 lines:
child process exited abnormally

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hi - i had some hold violations that were resolved by increasing

PL_RESIZER_HOLD_SLACK_MARGIN

, but now i'm trying to learn to interpret the timing report, and I see all clock network delays are zero (see thread). does this indicate that i have something misconfigured and the clock delays aren't getting modeled properly in the timing analysis?

Has anyone tried the FP_CONTEXT_DEF and FP_CONTEXT_LEF options? I was going through the OpenLane documentation when I read the following statements in the IO Placement section (https://github.com/The-OpenROAD-Project/OpenLane/blob/master/docs/source/hardening_macros.md#io-placement) _Using contextualized pin placement, which will automatically optimize the placement of the pins based on their context in the larger design that includes them. This relevant for macros since they will be included inside a core, and also relevant for the core since it will be part of a bigger chip. For this to happen, you need to point to the LEF and DEF of the container/parent design using these two variables: FP_CONTEXT_DEF and FP_CONTEXT_LEF. Note that currently this script can only handle the existance of a single instance of that macro._ Now I am a bit confused. How can we have the DEF/LEF of the parent module before generating the macros, instantiating them in the parent module, and running OpenLANE flow for the parent module. Or do we need to blackbox the macros, generate the DEF/LEF for the parent module and then proceed with hardening the macros, if we're following this approach?

I'm having problems with PDN generation. Can someone please tell me how to solve this problem? My design is at https://github.com/Hagiwara-shc/marmot_asic.git . It contains 14 SRAM macros under user_project_wrapper. When I make user_project_wrapper, it stops with the following error.

[WARNING PSM-0038] Unconnected PDN node on net vccd2 at location (388.800um, 1746.550um), layer: 5.
[WARNING PSM-0038] Unconnected PDN node on net vccd2 at location (205.200um, 1746.550um), layer: 5.
[WARNING PSM-0038] Unconnected PDN node on net vccd2 at location (210.600um, 1746.550um), layer: 5.
[ERROR]: PDN generation failed.
[ERROR]: You may need to adjust your macro placements or PDN  offsets/pitches to power all standard cell rails (or other PDN stripes)  in your design.

Hi everyone I was trying to update my openlane. When i run

make pull -openlane

I'm facing with error :

Before updating I was able to

make mount

but now Im not.

On the latest version of Openlane, I only see the summary of the stage being run whereas previously you could see the full output of every tool redirected to the terminal. This change is fine, but I'd prefer to enable full redirection of output. I can't find any option in the documentation to do this. Anyone have quick pointer before I dig into the tcl myself?

@User Any thoughts on https://github.com/Cloud-V/DFFRAM/issues/139? While my MPW5 tape out passes the STA checks, if I run STA of the entire design (including the RAMS) myself then I see the DFFRAM hold violations.

@User It's still not fixed.

Is it ok to submit design with 20 or so antenna violations? I realize this might affect yield, but for an mpw, will it be ok?

@User quite a few people I've been speaking to have had routing congestion issues with mpw5 tools as compared with previous versions. Do you know if anything substantial has changed?

After running make user_project_wrapper, I get the following warning. [WARNING]: All internal macros will not be connected to power. Does this look problematic? and if so what could be the root of the problem?

Hi everyone. I am trying to generate a macro in openlane that has multiple input clock frequencies. How can I set the variable CLOCK_PORT in the config.tcl file to accept multiple frequencies as input to the macro

After running make user_project_wrapper I get a plethora of DRC errors, as stated by @User, this is normal. However, the new gds, is not copied to the gds directory, but stays in the run directory. Is that normal? do we have to copy it manually? or am I getting some error, that is stopping some automatic copying

Hi, I am running openlane to make my updated user_project_wrapper.v around a small blackboxed module (col_driver.v), but running into LVS errors on LEF. Going by this discussion (https://skywater-pdk.slack.com/archives/C016H8WJMBR/p1647191149832239?thread_ts=1646668982.224529&cid=C016H8WJMBR), I pulled up my 30-user_project_wrapper.lef.log and see some confusion around power pins:

Subcircuit pins:
Circuit 1: user_project_wrapper            |Circuit 2: user_project_wrapper            
-------------------------------------------|-------------------------------------------
analog_io[3]                               |analog_io[3]                               
...
(no matching pin)                          |vccd1                                      
(no matching pin)                          |vssd1                                      
vccd1                                      |(no matching pin)                          
vssd1                                      |(no matching pin)

Why are power pins showing as having no matches? I am copying the same ifdef structure for defining power pins as in the counter example… Any help would be appreciated! cc: @User @User

Hi @User, I tested the latest updates to open_pdks and magic (with the fix for the inverted fringe capacitance calculation). It reduced the fmax of my design quite a lot vs a PDK from a month ago, but I guess that is to be expected since the reported capacitance along those paths are also much higher. What is a bit surprising is that the resizer didn't make an effort to fix it up. Makes me wonder if the RC estimates we use are reasonable. Do you know where these came from and if they look ok? https://github.com/RTimothyEdwards/open_pdks/blob/master/sky130/openlane/config.tcl#L143

Does yosys not support the synthesis of tri state buffers? I tried synthesising it and got the following error.

problem in openlane

Is it possible to use sky130_fd_sc_hvl with openlane? I want to make a design that has 3.3V for some parts of it.

@User can you recommend what to do here

Hi all, I am trying to run OpenLane using the

docker run

command, so I can run the container in the background and create a volume to access the results from the host machine. However, this command

docker run -it -v /home/anas/OpenLane:/openlane openlane

shows the following error message:

Unable to find image 'openlane:latest' locally
docker: Error response from daemon: Get "<https://registry-1.docker.io/v2/>": net/http: request canceled while waiting for connection (Client.Timeout exceeded while awaiting headers).
See 'docker run --help'.

Running OpenLane through

Make mount

is completely fine. I'm using Ubuntu WSL-2. Any help? Much appreciated. Anas

OpenLane install is failing on M1 MacBook (BTW, I am working in Parallels with ARM64, so I guess this same error would be there for any ARM64-based machine). When I do

make openlane

the following error shows up:

Step 1/25 : FROM openlane-run-base
pull access denied for openlane-run-base, repository does not exist or may require 'docker login': denied: requested access to the resource is denied

If I try to do

make pull-openlane

it fetches the prebuilt docker image, but fails later during

make pdk

with:

[ -d /home/parallels/OpenLane/pdks/sky130A ] && rm -rf /home/parallels/OpenLane/pdks/sky130A || true
docker run --rm -v /home/parallels/OpenLane:/openlane -v /home/parallels/OpenLane/designs:/openlane/install -v /home/parallels/OpenLane/pdks:/home/parallels/OpenLane/pdks -e PDK_ROOT=/home/parallels/OpenLane/pdks -e STD_CELL_LIBRARY=sky130_fd_sc_hd --user 1000:1000 -e DISPLAY=:0 -v /tmp/.X11-unix:/tmp/.X11-unix -v /home/parallels/.Xauthority:/.Xauthority --network host efabless/openlane:0d8d4c187cb6d0af7b221b364caa2908d8cc9843 sh -c "\
	cd /home/parallels/OpenLane/pdks/open_pdks && \
	./configure --enable-sky130-pdk=/home/parallels/OpenLane/pdks/skywater-pdk/libraries ""\
"
WARNING: The requested image's platform (linux/amd64) does not match the detected host platform (linux/arm64/v8) and no specific platform was requested
standard_init_linux.go:228: exec user process caused: exec format error
make: *** [dependencies/pdk.mk:72: build-pdk] Error 1

Dear all, can OpenLane work with VHDL-based source files? or I have to convert all VHDL files to Verilog? If so, are there any recommended VHDL-->Verilog converters? Thanks. Anas

I am running the openlane flow with mpw-5c tag and the flow fails after some DRCs

Run Directory: /home/mkhan33/openram_testchip/openlane/user_project_wrapper/runs/user_project_wrapper                                                                                
----------------------------------------                                                  

Magic DRC Summary:                                                                        
Source: /home/mkhan33/openram_testchip/openlane/user_project_wrapper/runs/user_project_wrapper/reports/finishing/drc.rpt                                                                                                                                                                                                                                                  
Violation Message "Metal4 > 3um spacing to unrelated m4 < 0.4um (met4.5b) "found 10 Times.                                                                                           
Violation Message "Metal3 > 3um spacing to unrelated m3 < 0.4um (met3.3d) "found 174 Times.                                                                                          
Violation Message "All nwells must contain metal-connected N+ taps (nwell.4) "found 5245 Times.                                                                                      
Total Magic DRC violations is 5429                                                        
----------------------------------------                                                  

LVS Summary:                                                                              
Source: /home/mkhan33/openram_testchip/openlane/user_project_wrapper/runs/user_project_wrapper/logs/finishing/37-user_project_wrapper.lvs.lef.log                                                                                                                                                                                                                         
LVS reports no net, device, pin, or property mismatches.                                                                                                                             
Total errors = 0                                                                          
----------------------------------------                                                  

Antenna Summary:                                                                          
No antenna report found.                                                                  
[INFO]: check full report here: /home/mkhan33/openram_testchip/openlane/user_project_wrapper/runs/user_project_wrapper/reports/final_summary_report.csv                                                                                                                                                                                                                   
[INFO]: Saving runtime environment...                                                     
[ERROR]: Flow failed.                                                                     
[INFO]: The failure may have been because of the following warnings:                                                                                                                 
[WARNING]: All internal macros will not be connected to power.                                                                                                                       
[WARNING]: All internal macros will not be connected to power.                                                                                                                       
[WARNING]: All internal macros will not be connected to power.                                                                                                                       


    while executing                                                                       
"flow_fail"                                                                               
    (procedure "quit_on_magic_drc" line 13)                                               
    invoked from within                                                                   
"quit_on_magic_drc -log $::env(drc_prefix).tr"                                            
    (procedure "run_magic_drc" line 31)                                                   
    invoked from within                                                                   
"run_magic_drc"                                                                           
    (procedure "run_drc_step" line 8)                                                     
    invoked from within                                                                   
"[lindex $step_exe 0] [lindex $step_exe 1] "                                              
    (procedure "run_non_interactive_mode" line 55)                                        
    invoked from within                                                                   
"run_non_interactive_mode {*}$argv"                                                       
    invoked from within                                                                   
"if { [info exists flags_map(-interactive)] || [info exists flags_map(-it)] } {                                                                                                      
        puts_info "Running interactively"                                                 
        puts_info "Note, that post_run_hook..."                                           
    (file "/openlane/flow.tcl" line 412)                                                  
make[1]: *** [Makefile:43: user_project_wrapper] Error 1                                                                                                                             
make[1]: Leaving directory '/home/mkhan33/openram_testchip/openlane'                                                                                                                 
make: *** [Makefile:69: user_project_wrapper] Error 2

I am not able to see a

final/verilog/gl

directory which has a GL netlist. I want to ignore these DRCs and run simulation on the GL. Is it possible?